Henrik RydgårdandClaude Opus 5.5 f8004442c8 RISC-V IR: Allocate the saved registers before the temporaries ...

After the registers usable by compressed instructions, prefer s2-s7 and
fs2-fs11, so that fewer values have to be flushed around calls. The
dispatcher already saves them.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>

2026-09-24 16:22:41 -06:00

..

RiscVAsm.cpp

Merge pull request #22336 from hrydgard/misc-work

2026-09-22 13:15:12 -06:00

RiscVCompALU.cpp

RISC-V JIT: Compile the bit ops and min/max without Zbb

2026-09-24 14:31:22 -06:00

RiscVCompBranch.cpp

x86jit: Stub out op categories to files.

2023-08-20 22:28:54 -07:00

RiscVCompFPU.cpp

RISC-V/LoongArch IR: Get vrot's sine and cosine from one call

2026-09-24 16:22:41 -06:00

RiscVCompLoadStore.cpp

irjit: Fix safety of kernel bit memory addresses.

2023-09-24 10:18:55 -07:00

RiscVCompSystem.cpp

RISC-V, LoongArch64: fix caller-saved FPRs, div by zero, and more

2026-09-22 08:39:25 -06:00

RiscVCompVec.cpp

IR: Fold ClampToZero into the 31-bit packs

2026-09-24 14:31:22 -06:00

RiscVJit.cpp

RISC-V, LoongArch64: fix caller-saved FPRs, div by zero, and more

2026-09-22 08:39:25 -06:00

RiscVJit.h

RISC-V JIT: Compile the bit ops and min/max without Zbb

2026-09-24 14:31:22 -06:00

RiscVRegCache.cpp

RISC-V IR: Allocate the saved registers before the temporaries

2026-09-24 16:22:41 -06:00

RiscVRegCache.h

irjit: Add facility for native reg transfer.

2023-09-24 16:28:29 -07:00