Henrik Rydgård 951c35ba71 Merge pull request #17948 from unknownbrackets/x86-ir ...

x86jit: Fix some issues in 32-bit

2023-08-22 09:41:10 +02:00

..

RiscVAsm.cpp

riscv: Use a single reg cache.

2023-08-20 12:42:11 -07:00

RiscVCompALU.cpp

riscv: Use a single reg for LO/HI.

2023-08-20 14:49:09 -07:00

RiscVCompBranch.cpp

x86jit: Stub out op categories to files.

2023-08-20 22:28:54 -07:00

RiscVCompFPU.cpp

x86jit: Stub out op categories to files.

2023-08-20 22:28:54 -07:00

RiscVCompLoadStore.cpp

riscv: Mark normalized32 after mapping.

2023-08-20 12:42:11 -07:00

RiscVCompSystem.cpp

riscv: Use automapping for special cases too.

2023-08-20 12:42:11 -07:00

RiscVCompVec.cpp

riscv: Use automapping for special cases too.

2023-08-20 12:42:11 -07:00

RiscVJit.cpp

x86jit: Improve debug disasm.

2023-08-20 22:28:54 -07:00

RiscVJit.h

riscv: Use a single reg cache.

2023-08-20 12:42:11 -07:00

RiscVRegCache.cpp

x86jit: Automatically flush incompatible regs.

2023-08-21 21:16:54 -07:00

RiscVRegCache.h

x86jit: Automatically flush incompatible regs.

2023-08-21 21:16:54 -07:00