ppsspp

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Henrik Rydgård 3ef6ad6285 arm64jit: Don't sign-extend constant addresses with the top bit set

The ARM64 IR JIT crashed on any load/store to a constant address with the
top bit set and an offset too large for an immediate - the kernel RAM mirror
at 0x88000000, for instance.

PrepareSrc1Address is careful about this: a constant address like 0x89100010
arrives sign-extended as a negative int64_t, and the (imm & 0xC0000000) ==
0x80000000 check turns it back into the positive value it should be. But when
the offset doesn't fit an immediate we fall back to loading it into a register
and using the register-offset addressing mode, which only takes the W half of
that register plus an extend - and we asked for SXTW, undoing the fix and
pointing the access ~2GB below the memory view.

Sign extension is still right when the offset is genuinely negative, which
happens when the base is a pointerified register and the displacement is a
negative one from the MIPS instruction. So extend based on the sign of imm.

Found by the Jit unit test, which stores to 0x89100000 and segfaults in the
JIT_IR phase - only reproducible on an actual ARM64 CPU, which is why it never
showed up on CI. The RISC-V and LoongArch backends get this case right already.

2026-09-02 17:53:12 +02:00

Arm64Asm.cpp

Add a utility function for all the ABIs to call functions with a pointer arg. Use to call Advance from the JIT with the MIPSContext. Indent some code better.

2026-08-13 08:09:30 +02:00

Arm64CompALU.cpp

Code cleanup. Don't use gpr.SetRegImm where all we do is write to a scratch register

2026-02-10 19:28:53 +01:00

Arm64CompBranch.cpp

Plumb through the PC value for syscalls, so we can get better diagnostics for unresolved ones.

2026-08-15 19:14:13 +02:00

Arm64CompFPU.cpp

Implement MMIO for the JIT (by falling back to the interpreter for load/stores from kernel addresses)