Henrik Rydgård ba148e5ec7 JIT/IRJit: Delete an old "function preloading" experiment ...

This caused some confusion while trying to debug #20502

2025-06-11 15:45:18 +02:00

..

RiscVAsm.cpp

Move more core-related stuff into Core.cpp/h

2024-12-08 11:54:58 +01:00

RiscVCompALU.cpp

riscv: Use a single reg for LO/HI.

2023-08-20 14:49:09 -07:00

RiscVCompBranch.cpp

x86jit: Stub out op categories to files.

2023-08-20 22:28:54 -07:00

RiscVCompFPU.cpp

riscv: Implement Zfa encoding.

2023-12-29 09:42:23 -08:00

RiscVCompLoadStore.cpp

irjit: Fix safety of kernel bit memory addresses.

2023-09-24 10:18:55 -07:00

RiscVCompSystem.cpp

Split Core_EnableStepping into Core_Break and Core_Resume

2024-11-03 17:53:42 +01:00

RiscVCompVec.cpp

riscv: Implement Zfa encoding.

2023-12-29 09:42:23 -08:00

RiscVJit.cpp

JIT/IRJit: Delete an old "function preloading" experiment

2025-06-11 15:45:18 +02:00

RiscVJit.h

JIT/IRJit: Delete an old "function preloading" experiment

2025-06-11 15:45:18 +02:00

RiscVRegCache.cpp

Logging API change (refactor) (#19324)

2024-07-14 14:42:59 +02:00

RiscVRegCache.h

irjit: Add facility for native reg transfer.

2023-09-24 16:28:29 -07:00