Henrik RydgårdandClaude Opus 5.5 e0a31e7fbc VFPU: Generate the VFPU's NaN in vbfy, vocp and vsocp on all cores ...

These are sums, so a NaN result is 0x7F800001 like vadd's (cpu/vfpu/specials).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

2026-10-14 11:47:33 +02:00

..

Arm64Asm.cpp

Keep JIT block entries and replacement hooks out of PSP memory

2026-10-11 10:33:30 +02:00

Arm64CompALU.cpp

Decode the unused bits of shifts and Allegrex bit ops as the PSP does

2026-10-14 10:56:48 +02:00

Arm64CompBranch.cpp

Plumb through the PC value for syscalls, so we can get better diagnostics for unresolved ones.

2026-08-15 19:14:13 +02:00

Arm64CompFPU.cpp

ARM JITs: Mask what ctc1 writes to fcr31

2026-09-29 11:09:47 -06:00

Arm64CompLoadStore.cpp

Core: Let 16-bit CPU accesses through the depth mirrors see the GE's layout

2026-10-08 18:37:23 +02:00

Arm64CompReplace.cpp

cmake: Detect features at compile time

2016-10-19 12:31:19 +02:00

Arm64CompVFPU.cpp

VFPU: Generate the VFPU's NaN in vbfy, vocp and vsocp on all cores

2026-10-14 11:47:33 +02:00

Arm64IRAsm.cpp

Keep JIT block entries and replacement hooks out of PSP memory

2026-10-11 10:33:30 +02:00

Arm64IRCompALU.cpp

arm64 IR JIT: divu by zero compared the numerator signed

2026-09-22 11:02:20 -06:00

Arm64IRCompBranch.cpp

arm64jit: Implement exits.

2023-09-03 21:16:08 -07:00

Arm64IRCompFPU.cpp

VFPU: Produce the PSP's NaNs in the single-lane ops, on every core

2026-10-14 11:47:33 +02:00

Arm64IRCompLoadStore.cpp

IR native backends: Fix ll into $zero, and sc losing its result

2026-10-14 00:10:00 +02:00

Arm64IRCompSystem.cpp

Plumb through the PC value for syscalls, so we can get better diagnostics for unresolved ones.

2026-08-15 19:14:13 +02:00

Arm64IRCompVec.cpp

VFPU: Produce the PSP's NaNs in the single-lane ops, on every core

2026-10-14 11:47:33 +02:00

Arm64IRJit.cpp

Keep JIT block entries and replacement hooks out of PSP memory

2026-10-11 10:33:30 +02:00

Arm64IRJit.h

arm64 IR JIT: Pair adjacent loads and stores into LDP/STP

2026-09-25 11:47:17 -06:00

Arm64IRRegCache.cpp

IR JIT: Don't store dead temps at exits

2026-09-24 16:38:39 -06:00

Arm64IRRegCache.h

arm64jit: Implement reg lane transfers.

2023-09-30 15:44:41 -07:00

Arm64Jit.cpp

JITs: Notice a rounding mode that didn't come from a compiled ctc1

2026-10-14 09:26:28 +02:00

Arm64Jit.h

VFPU: Produce the PSP's NaNs in the single-lane ops, on every core

2026-10-14 11:47:33 +02:00

Arm64RegCache.cpp

More fixes, more gamescreen button fixes

2026-02-12 01:35:57 +01:00

Arm64RegCache.h

Remove more vestiges of old experiments

2026-02-12 01:23:48 +01:00

Arm64RegCacheFPU.cpp

arm64 JIT: Keep S8-S15 mapped across VFPU math calls

2026-09-24 16:22:22 -06:00

Arm64RegCacheFPU.h

arm64 JIT: Keep S8-S15 mapped across VFPU math calls

2026-09-24 16:22:22 -06:00