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Author SHA1 Message Date
Henrik Rydgård f3c89e49f0 Merge pull request #17778 from hrydgard/new-icons 
Add some new UI icons
 2023-07-24 15:49:38 +02:00
Henrik Rydgård fecd0b8cd7 Use the new play button icon in the retroachievement sound customizer 2023-07-24 14:56:35 +02:00
Henrik Rydgård 2baba83f1a Add a bunch of new icon images to the atlas. 2023-07-24 14:52:32 +02:00
Henrik Rydgård 3c2f67a097 Merge pull request #17777 from hrydgard/fix-achievements-from-frontend 
RetroAchievements: Fix another race condition, improve logging.
 2023-07-24 12:37:40 +02:00
Henrik Rydgård a72c4aa383 Actually fix the race condition. Can't do any initialization step while waiting. 2023-07-24 12:08:15 +02:00
Henrik Rydgård 3ae520c35d RetroAchievements: Fix another race condition, improve logging. 
Seems to help the frontend problem.
 2023-07-24 12:00:16 +02:00
Henrik Rydgård bee2400230 Merge pull request #17769 from unknownbrackets/vertexjit-debug 
Add compilation-enabled vertexjit compare tool
 2023-07-24 09:39:52 +02:00
Henrik Rydgård c697dca3e0 Merge pull request #17776 from unknownbrackets/riscv-vertexjit 
Correct a few more RISC-V vertexjit bugs
 2023-07-24 09:13:17 +02:00
Unknown W. Brackets b6f83ca969 riscv: Cleanup some pointerification flags. 2023-07-23 21:17:55 -07:00
Unknown W. Brackets 18c48681a8 riscv: Implement multiply instructions. 2023-07-23 18:01:50 -07:00
Unknown W. Brackets 7f4689e8fa riscv: Use direct SLI/SLIU instructions. 
Derp, I forgot these existed on RISC-V for a moment.
 2023-07-23 18:01:46 -07:00
Unknown W. Brackets ca15fa7061 riscv: Enable jit by default. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 4100767b5e riscv: Optimize SetConst a bit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets f7f7531500 riscv: Fix min/max normalization. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 34bfe93ea5 riscv: Fix block lookup issues. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 92694e765f riscv: Implement conditional moves. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 2c7da94bd1 riscv: Implement shifts and compares. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 5ed2f0d559 riscv: Implement logic ops. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 94be343591 riscv: Try to keep regs normalized, track. 
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 7aafa11d24 riscv: Implement conditional exits. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 8ee73264bf riscv: Correct depointerify on FlushAll(). 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 720f868a10 riscv: Use R_RA as a temporary for calls. 
This is the most logical thing, since we're about to write it anyway.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 76e3246065 riscv: Reduce jit codesize a bit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets d31eded9ba riscv: Allow dirty pointers, explicitly. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 624caa2dea riscv: Implement the simplest exits. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 1dfedde741 riscv: Avoid needless save/load around compile. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 165169eb31 riscv: Implement load and store ops. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets c2da7d18bb riscv: Stub out more IR compilation categories. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 05a2789cf4 riscv: Implement some simple assign instructions. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets c6c25af484 riscv: Add some safety to pointerifying. 
We have to clear the upper bits in case of sign extension or other things.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets bf7a6eb2cd riscv: Add jit for some initial instructions. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 4c1cc2dfdc riscv: Add a register cache for jit. 
Not yet actually used.  Might be buggy.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets b2d3c750f1 irjit: Define a specific IRReg type. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 47b81985bd riscv: Initial untested dispatcher. 
The minimum to actually, probably, running code.  Pretty slow.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets e271e43ec5 riscv: Initial staffolding for IR based jit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 3468423bb4 Debugger: Handle missing crash/block ptrs better. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets b041e712de riscv: Fix signed position bug in vertexjit. 2023-07-23 17:57:08 -07:00
Unknown W. Brackets 5cbad1982b riscv: Correct 565 morph mistake. 
Observed ni Valkyria Chronicles 3.
 2023-07-23 17:57:08 -07:00
Henrik Rydgård b7bcba16c8 Merge pull request #17774 from GABO1423/ppsspp-en-español 
(Lang) Tweak Spanish Translations
 2023-07-24 01:51:28 +02:00
Henrik Rydgård 0f2ccc3bc0 Merge pull request #17775 from hrydgard/unknownbrackets-cmake 
Linux: Use _DEFAULT_SOURCE
 2023-07-24 01:50:20 +02:00
Unknown W. Brackets 021aa319d5 Linux: Use _DEFAULT_SOURCE. 
Needed for gettimeofday() etc.  Keeping _BSD_SOURCE for now for compatibility.
 2023-07-23 16:12:26 -07:00
GABO1423 6ce3ebc9c9 (Lang) Tweak Spanish Translations 2023-07-23 19:11:00 -04:00
Henrik Rydgård add3a6b01d Merge pull request #17772 from hrydgard/fix-achievements-from-frontend 
Fix issue where achievements wouldn't always activate when starting from frontends
 2023-07-24 00:12:40 +02:00
Henrik Rydgård a3d52ec123 Merge pull request #17773 from unknownbrackets/riscv-emit 
Fix some issues in the RISC-V emitter
 2023-07-24 00:06:15 +02:00
Henrik Rydgård 95fd2eb7d3 Merge pull request #17767 from hrydgard/translation-consolidation 
Translation: Consolidate a few strings
 2023-07-24 00:04:07 +02:00
Henrik Rydgård da2b31e2cc Merge pull request #17771 from unknownbrackets/riscv-vertexjit 
Fix some silly mistakes in the RISC-V vertexjit
 2023-07-23 23:57:04 +02:00
Henrik Rydgård 0afd313371 Merge pull request #17770 from unknownbrackets/http-proxy-hang 
http: Fix hang on early close
 2023-07-23 23:56:07 +02:00
Henrik Rydgård 89d5f55893 Merge pull request #17768 from unknownbrackets/vertex-uvscale 
GPU: Correct UV scale for non-jit vertices
 2023-07-23 23:52:20 +02:00
Unknown W. Brackets 030a27f15d riscv: Stop considering bitmanip "B". 
Apparently it's not being called B anymore and B is still reserved.
 2023-07-23 14:41:08 -07:00
Unknown W. Brackets e0eace505b riscv: Fix cases of SetRegToImmediate(). 
Was using the wrong value for AUIPC, causing assertion failures and wrong
values.  Also needed to handle sign-extend more carefully.
 2023-07-23 14:41:08 -07:00