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12833 Commits
Author SHA1 Message Date
Henrik Rydgård 5dcd14b17a Merge pull request #17901 from unknownbrackets/riscv-disasm 
riscv: Add debug log of block disasm
 2023-08-13 21:07:37 +02:00
Unknown W. Brackets f03cd0b2ad Merge pull request #17899 from unknownbrackets/riscv-minor 
Minor RISC-V cleanups, frame profiler fix
 2023-08-13 11:19:42 -07:00
Henrik Rydgård d6cdb6e5d9 Merge pull request #17900 from unknownbrackets/irjit-vsgelt 
irjit: Implement vsge/vslt
 2023-08-13 19:59:14 +02:00
Unknown W. Brackets 23c79f8e7f irjit: Implement vsge/vslt. 
These are not ideal especially for SIMD, but they do work.
Improves performance in Silent Hill on RISC-V by like 20%.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets 5d20f2aabd irjit: Simplify VecDo3. 2023-08-13 10:40:47 -07:00
Unknown W. Brackets 2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg. 
We already have a zero reg, so this is more useful and symmetrical.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets 2bb67db43c riscv: Switch to the logBlocks model for disasm. 2023-08-13 10:37:21 -07:00
Unknown W. Brackets 8c036a889d riscv: Add debug log of block disasm. 2023-08-13 10:32:04 -07:00
Unknown W. Brackets 7cc6c5fa62 riscv: Fix load error w/o pointerify. 2023-08-13 10:20:28 -07:00
Unknown W. Brackets be938a850b riscv: Remove FMul safety check. 
Let's just see if everything's right, this bloats multiplies a lot.
Doesn't seem to impact perf a lot, though.
 2023-08-13 10:20:20 -07:00
Unknown W. Brackets fa53b80574 irjit: Cleanup/purge FPU/VFPU temps. 
A lot of cases are followed by an FMov that just moved the temp to a
regular register, from VFPU instructions playing safe about overlaps.
 2023-08-13 10:14:10 -07:00
Henrik Rydgård 7bb1914fd3 Add FrameTiming.cpp/h (with no real contents) 2023-08-13 17:57:43 +02:00
Henrik Rydgård 2a74a0b98a Merge pull request #17893 from unknownbrackets/riscv-blocklink 
riscv: Enable block linking
 2023-08-13 12:40:39 +02:00
Ethan O'Brien 8426b35a80 Cleanup emscripten libretro build target 2023-08-12 14:38:35 -05:00
Unknown W. Brackets 81f67c717c riscv: Fix block link for prev blocks. 
Oops, was just reversed so never linking.
 2023-08-12 10:48:39 -07:00
Unknown W. Brackets fcc90095f7 riscv: Enable block linking. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets 247788806a irjit: Add direct helper for start PC. 
It's annoying always fetching length too.
 2023-08-12 09:37:02 -07:00
Unknown W. Brackets b3cdf06c5a riscv: Write fixup on block invalidation. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets 3757ebca2d irjit: Invalidate/finalize target blocks. 
Doesn't actually do anything yet, but adds plumbing.
 2023-08-12 09:37:02 -07:00
Henrik Rydgård 1ea11c233c Remove "SwapBuffers" from the GraphicsContext interface. 
Buildfixes

More buildfix

headless buildfix

One more buildfix
 2023-08-11 01:57:02 +02:00
Henrik Rydgård 7c60022979 Fix hang after exiting a game. After running a game, coreState is POWERDOWN which counts as stepping. 2023-08-10 23:52:24 +02:00
Henrik Rydgård 779a156251 PortManager warning fix. The #pragma pack stuff was redundant anyway 2023-08-10 17:15:57 +02:00
Henrik Rydgård 4b0ac494d0 Even more simplification 2023-08-10 17:15:57 +02:00
Henrik Rydgård 0477ba8c78 Core.cpp: Some slight simplifications 2023-08-10 17:15:56 +02:00
Henrik Rydgård be708e3e02 Move KeepScreenAwake to platform specific code. 2023-08-10 16:12:12 +02:00
Henrik Rydgård 50ea506b6a Revert "Regression experiment: Temporarily revert to returning 0 from bad achievement memory accesses." 
This reverts commit a044d8ccc2.
 2023-08-09 16:16:39 +02:00
Henrik Rydgård 2342c4522c Merge pull request #17875 from unknownbrackets/riscv-jit 
RISC-V: Implement a few more ops
 2023-08-09 09:30:15 +02:00
Henrik Rydgård bac4e8d42d Merge pull request #17874 from unknownbrackets/irjit-exits 
IR: Simplify exits to ExitToConst when viable
 2023-08-09 09:11:52 +02:00
Henrik Rydgård 6758675054 Merge pull request #17873 from unknownbrackets/irjit-shuffle 
IR: Fix vqmul / Vec4Shuffle overlap
 2023-08-09 09:10:03 +02:00
Unknown W. Brackets 2c13b6d973 riscv: Implement vc2i. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 28c58c1d24 irjit: Allow more forms of vmidt. 
Mildly worth it.
 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 4b9011e475 riscv: Reduce call bloat using temps. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets ddf3d02a3c riscv: Implement vi2uc. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 268adf1aa1 riscv: Implement scaled float/int convert. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 0b4e7d60f9 riscv: Implement ReverseBits in jit. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets ad4cbbab8e riscv: Don't cache mipState on backend. 
Bad sign if we're trying to use it, anyway.
 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 31ff23746c irjit: Prefer ExitToConst over ExitToReg. 2023-08-08 23:14:01 -07:00
Unknown W. Brackets 3f97545f99 irjit: Reduce exits from constants. 
This reduces bloat a bit, and may help with common funcs that enter short
loops.
 2023-08-08 23:05:14 -07:00
Unknown W. Brackets 5f9a8fd1a1 irjit: Rename IRRegCache to IRImmRegCache. 
For clarity, since it's not a native regcache.
 2023-08-08 23:05:14 -07:00
Unknown W. Brackets 1a92027810 riscv: Make Vec4Shuffle overlap safe. 2023-08-08 23:00:45 -07:00
Unknown W. Brackets e73c203984 irjit: Fix Vec4Shuffle overlap issue. 2023-08-08 23:00:39 -07:00
Henrik Rydgård ac269aaa4b rcheevos: revert to before #17806 
PR #17806 upgraded rcheevos, after which a regression is reported in
issue #17631.

Experimentally revert to confirm.
 2023-08-08 15:38:22 +02:00
Henrik Rydgård a044d8ccc2 Regression experiment: Temporarily revert to returning 0 from bad achievement memory accesses. 2023-08-08 15:33:46 +02:00
Henrik Rydgård 5ee04ce403 SDL: Break out event processing from main loop 
Makes things a bit easier to work with.
 2023-08-08 12:28:42 +02:00
Henrik Rydgård bcae36d8cb Merge NativeUpdate and NativeRender, we always call them together. 2023-08-07 22:50:57 +02:00
Henrik Rydgård 096c168dd7 Add yield() function to tell the CPU that we're busy-waiting (rare) (#17862) 
* Add yield() function to tell the CPU that we're busy-waiting (rare)

Use it only for the busy-wait in lag sync, which only happens in
Windows.

* Buildfix attempt
 2023-08-07 21:38:03 +02:00
Henrik Rydgård e9431d0d1e Merge pull request #17859 from unknownbrackets/irjit-vec4 
irjit: Use Vec4 a bit more
 2023-08-06 23:05:33 +02:00
Unknown W. Brackets 3dc71cff75 irjit: Keep a couple more ops in Vec4. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets 6a1dbd4cde irjit: Allow Vec4 to be used with masks. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets 2b964fd3b0 irjit: Handle more common Vec4 prefix cases. 2023-08-06 13:38:00 -07:00