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39,166 Commits 98 Branches 131 Tags
ca94de8d4b1e53b7d596d31e7336ac5133a32a7c
Commit Graph
142 Commits
Author SHA1 Message Date
Herman Semenov b871e76d05 [Core/Debugger/FileLoaders/FileSystems/MIPS] Using reserve if possible 2023-12-15 13:59:19 +03:00
Unknown W. Brackets 00c80cea6e irjit: Optimize offset logging during compile. 
As I guessed, this was expensive.  using a vector and reserve isn't very.
It's nice to keep this before logBlocks_ is > 0, in case it's set mid
block.
 2023-09-30 15:56:18 -07:00
Henrik Rydgård 9fffa33eee Merge pull request #18234 from unknownbrackets/x86-ir-transfer 
x86jit: Perform vector transfers instead of flushing to memory
 2023-09-26 09:28:05 +02:00
Unknown W. Brackets 9b2fa46861 IR: Add mini native jit MIPS block profiler. 2023-09-24 23:04:29 -07:00
Unknown W. Brackets 88b6442527 irjit: Add facility for native reg transfer. 2023-09-24 16:28:29 -07:00
Unknown W. Brackets 7d0f2e43b6 irjit: Fix safety of kernel bit memory addresses. 2023-09-24 10:18:55 -07:00
Unknown W. Brackets 14e2e1ed62 x64jit: Optimize FCmpVfpuAggregate. 2023-09-23 14:31:46 -07:00
Unknown W. Brackets 7a5cdafdf3 arm64jit: Implement convert/int conversions. 2023-09-08 00:03:12 -07:00
Henrik Rydgård 0a234df037 Merge pull request #18089 from unknownbrackets/arm64jit-float 
arm64jit: Implement VFPU compare, trig, couple others
 2023-09-08 08:33:22 +02:00
Nemoumbra 0faa1109d2 Included <algorithm> for std::min 2023-09-07 12:14:36 +03:00
Unknown W. Brackets a1304f6ac8 arm64jit: Implement VFPU compare in IR. 2023-09-06 19:02:24 -07:00
Unknown W. Brackets 97d9a7f07f arm64jit: Implement FCmp. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets 81aeb04788 arm64jit: Implement Vec4Blend. 2023-09-05 00:10:26 -07:00
Henrik Rydgård 9690a71a14 Merge pull request #18061 from unknownbrackets/arm64-ir-jit 
arm64jit: Implement most ALU and load/store in IR jit
 2023-09-04 10:02:24 +02:00
Unknown W. Brackets 85b80bc9e5 arm64jit: Implement load/store in IR. 2023-09-04 00:04:36 -07:00
Unknown W. Brackets e02426cbbf arm64jit: Implement some system ops. 2023-09-03 21:16:08 -07:00
Henrik Rydgård 2f300c2023 Merge pull request #18060 from unknownbrackets/x86-jitbase 
x86jit: Bake emuhack mask into jitbase
 2023-09-03 22:53:23 +02:00
Unknown W. Brackets 9439a43323 riscv: Correct an overlap case, fix assert. 2023-09-03 13:29:57 -07:00
Unknown W. Brackets 0452b8b57a riscv: Account for emuhack in JITBASEREG. 2023-09-03 13:29:05 -07:00
Unknown W. Brackets 1d152a1486 x86jit: Bake emuhack mask into jitbase. 2023-09-03 12:49:36 -07:00
Unknown W. Brackets 1b756ff8c1 arm64jit: Add initial base for IR jit. 
This works, but very slowly at this point.
 2023-09-03 12:14:28 -07:00
Henrik Rydgård dddf63d057 Merge pull request #17993 from unknownbrackets/x86-jit-minor 
x86jit: Replacements, expose for profiling better
 2023-08-28 10:23:00 +02:00
Unknown W. Brackets 61a99b4bac x86jit: Implement trig/reciprocals. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets 4b1c809886 x86jit: Implement a few more float ops, shuffle. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets 2e64abd2a0 x86jit: Improve some debug labels. 
Helps when running a profiler that reads these.
 2023-08-27 12:51:29 -07:00
Henrik Rydgård 951c35ba71 Merge pull request #17948 from unknownbrackets/x86-ir 
x86jit: Fix some issues in 32-bit
 2023-08-22 09:41:10 +02:00
Unknown W. Brackets 07fa1ed573 x86jit: Automatically flush incompatible regs. 2023-08-21 21:16:54 -07:00
Unknown W. Brackets db34b85107 irjit: Allow flag-based allocation order. 
Sometimes backends have needs, like XMM0/v0-only, or similar.
 2023-08-21 20:46:05 -07:00
Henrik Rydgård 1e269c1d3c Merge pull request #17943 from unknownbrackets/x86-ir 
Add an x86/x64 backend for IR
 2023-08-21 09:21:37 +02:00
Unknown W. Brackets 08ea31f405 x86jit: Improve debug disasm. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 4e3f3860f9 x86jit: Stub out op categories to files. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets c491f701ba x86jit: Add initial IR-based jit backend. 
It works, but pretty slow in some parts with everything stubbed.
 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 8dfc2f04d7 riscv: Use a single reg for LO/HI. 
This is the same optimization we have for arm64, basically.
 2023-08-20 14:49:09 -07:00
Unknown W. Brackets 36b6aa4728 riscv: Allow GPR "SIMD" without FPR SIMD. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets 6a75e6712e riscv: Use automapping for special cases too. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets a190793ad2 riscv: Simplify mapping for more instructions. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets cc4bc406d5 riscv: Cleanup VfpuCtrlToReg meta, use auto-map. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets e40ae60029 riscv: Mark normalized32 after mapping. 
It's less confusing to separate it.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets f9bf7de701 riscv: Use a single reg cache. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets e30fb82a64 riscv: Remove some unused reg funcs. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets a23ade8f75 riscv: Map IR regs based on metadata. 
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets 161465ab66 riscv: Centralize register FlushAll(). 2023-08-19 21:30:03 -07:00
Unknown W. Brackets f3d4bd8c11 riscv: Centralize reg-as-pointer. 2023-08-19 21:24:36 -07:00
Unknown W. Brackets 92f7374c89 riscv: Centralize reg mapping itself. 2023-08-19 16:15:49 -07:00
Unknown W. Brackets 718a1b3944 riscv: Centralize MarkDirty flagging. 2023-08-19 16:15:49 -07:00
Unknown W. Brackets 4e41f83ecc riscv: Centralize IR reg cache metadata checks. 
These are all largely the same between backends.
 2023-08-17 23:03:31 -07:00
Unknown W. Brackets ebab0e1591 riscv: Centralize reg allocation. 2023-08-17 18:50:33 -07:00
Unknown W. Brackets b30daa5760 riscv: Centralize state of regcaches. 2023-08-15 21:51:38 -07:00
Henrik Rydgård a7bc70834c Merge pull request #17907 from unknownbrackets/riscv-minor 
riscv: Implement vs2i
 2023-08-14 07:41:45 +02:00
Unknown W. Brackets 52cc38bf2a riscv: Implement vs2i. 2023-08-13 18:27:19 -07:00