5 Commits

Include renames

Author	SHA1	Message	Date
Henrik RydgårdandClaude Opus 5.5	d71599ae85	RISC-V emitter: Fix the vmv.s.x and vfmv.s.f encodings ... They used the OPMVV and OPFVV funct3, which makes them vmv.x.s and vfmv.f.s: the scalar register was written instead of the vector. Nothing used them until now. Checked against GNU as. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>	2026-10-15 14:42:00 +02:00
Henrik RydgårdandClaude Opus 5.5	ae32504fa1	RISC-V emitter: Fix Zcb byte offsets, and FLI of a NaN ... c.lbu and c.sb keep the offset's bit 0 in bit 6 and bit 1 in bit 5, so offsets 1 and 2 were swapped, and the JIT loaded and stored the wrong byte. FLI's only NaN is the canonical one, but CanFLI took any NaN for it: the pattern went through a float to double conversion that quieted it, which on RISC-V also drops the sign and payload. vfim of a NaN lost its sign. Neither is detected on real hardware yet (we never set Zcb or Zfa), and the CPU fuzzer found both with the extensions forced on under qemu. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>	2026-10-15 14:41:51 +02:00
Henrik Rydgård	9218fe9b59	Rework the shutdown logic in the OpenGL backend. Eliminated race conditions.	2025-08-31 10:57:06 +02:00
Unknown W. Brackets	77849d3eed	riscv: Add disassembler. ... From https://github.com/anthony-coulter/riscv-disassembler. Modified slightly to pull in less headers in the h, prefix funcs.	2023-01-01 10:28:53 -08:00
Unknown W. Brackets	216fcb228c	riscv: Add a simple unit test. ... Since I haven't tried running these yet, at least best to validate...	2022-08-28 06:03:31 -07:00