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RISC-V emitter: Fix the vmv.s.x and vfmv.s.f encodings

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They used the OPMVV and OPFVV funct3, which makes them vmv.x.s and vfmv.f.s: the scalar register
was written instead of the vector. Nothing used them until now. Checked against GNU as.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
This commit is contained in:
Henrik RydgårdandClaude Opus 5.5 committed 2026-10-15 14:42:00 +02:00
1 parent fe2c9a3231
commit d71599ae85
2 files changed
+29 -2
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Common/RiscVEmitter.cpp
+2 -2
View File
@@ -3923,7 +3923,7 @@ void RiscVEmitter::VMV_X_S(RiscVReg rd, RiscVReg vs2) {
void RiscVEmitter::VMV_S_X(RiscVReg vd, RiscVReg rs1) {
_assert_msg_(IsVPR(vd), "%s instruction vd must be VPR", __func__);
_assert_msg_(IsGPR(rs1), "%s instruction rs1 must be GPR", __func__);
Write32(EncodeV(vd, Funct3::OPMVV, rs1, V0, VUseMask::NONE, Funct6::VRWUNARY0));
Write32(EncodeV(vd, Funct3::OPMVX, rs1, V0, VUseMask::NONE, Funct6::VRWUNARY0));
}
void RiscVEmitter::VFMV_F_S(RiscVReg rd, RiscVReg vs2) {
@@ -3936,7 +3936,7 @@ void RiscVEmitter::VFMV_S_F(RiscVReg vd, RiscVReg rs1) {
_assert_msg_(FloatBitsSupported() >= 32, "FVV instruction requires vector float support");
_assert_msg_(IsVPR(vd), "%s instruction vd must be VPR", __func__);
_assert_msg_(IsFPR(rs1), "%s instruction rs1 must be FPR", __func__);
Write32(EncodeV(vd, Funct3::OPFVV, rs1, V0, VUseMask::NONE, Funct6::VRWUNARY0));
Write32(EncodeV(vd, Funct3::OPFVF, rs1, V0, VUseMask::NONE, Funct6::VRWUNARY0));
}
void RiscVEmitter::VSLIDEUP_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
unittest/TestRiscVEmitter.cpp
+27
View File
@@ -98,6 +98,33 @@ bool TestRiscVEmitter() {
EXPECT_EQ_HEX(code16[i], expectedZcb[i]);
}
// Moves between a vector's first element and a scalar register.
cpu_info.RiscV_V = true;
emitter.SetCodePointer((u8 *)code, (u8 *)code);
emitter.VMV_S_X(V7, R_ZERO);
emitter.VMV_S_X(V1, X10);
emitter.VFMV_S_F(V7, F10);
emitter.VMV_X_S(X10, V5);
emitter.VFMV_F_S(F10, V5);
emitter.VMV_VI(V3, -1);
// From GNU as.
static constexpr uint32_t expectedV[] = {
0x420063d7,
0x420560d7,
0x420553d7,
0x42502557,
0x42501557,
0x5e0fb1d7,
};
len = (u32 *)emitter.GetWritableCodePtr() - code;
EXPECT_EQ_INT(len, ARRAY_SIZE(expectedV));
for (ptrdiff_t i = 0; i < len; ++i) {
EXPECT_EQ_HEX(code[i], expectedV[i]);
}
// FLI has only the canonical NaN.
cpu_info.RiscV_Zfa = true;
EXPECT_TRUE(emitter.CanFLI(32, (uint32_t)0x7FC00000));