 Henrik Rydgård
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6a3840d9b6
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Implement bswap just because
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2023-08-22 16:18:03 +02:00 |
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Henrik Rydgård
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7384d3d49f
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Debug mode buildfix
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2023-08-22 16:15:07 +02:00 |
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Henrik Rydgård
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c5a076487e
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Disable extends on x86-32
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2023-08-22 16:09:45 +02:00 |
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Henrik Rydgård
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b67741509c
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Implement a few ALU ops in the x86 JIT-from-IR.
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2023-08-22 16:08:12 +02:00 |
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Unknown W. Brackets
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11c40e6889
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x86: Implement a few basic float/vec4 ops.
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2023-08-22 10:39:46 +02:00 |
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Unknown W. Brackets
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521b63dd2b
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x86jit: Implement FMul.
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2023-08-22 10:39:46 +02:00 |
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Unknown W. Brackets
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edcb156897
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x86jit: Add Vec4 and Float load/store.
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2023-08-22 10:39:46 +02:00 |
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Henrik Rydgård
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951c35ba71
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Merge pull request #17948 from unknownbrackets/x86-ir
x86jit: Fix some issues in 32-bit
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2023-08-22 09:41:10 +02:00 |
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Unknown W. Brackets
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07fa1ed573
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x86jit: Automatically flush incompatible regs.
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2023-08-21 21:16:54 -07:00 |
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Unknown W. Brackets
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55654f52b2
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x86jit: Fix Store8 on i386.
Require an 8-bit capable register in mapping.
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2023-08-21 21:05:51 -07:00 |
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Unknown W. Brackets
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db34b85107
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irjit: Allow flag-based allocation order.
Sometimes backends have needs, like XMM0/v0-only, or similar.
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2023-08-21 20:46:05 -07:00 |
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Unknown W. Brackets
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bea74ba162
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x86jit: Avoid negative offset warning.
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2023-08-21 20:38:56 -07:00 |
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ANR2ME
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3c66523f04
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A quick fix for Metal Gear Acid due to adhocctl's busy state never reset to false when there are no adhocctl's handler.
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2023-08-22 04:29:07 +07:00 |
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Unknown W. Brackets
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1ccc2d5d2f
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x86jit: Fix address offsets with memview mask.
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2023-08-21 09:03:10 -07:00 |
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Unknown W. Brackets
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40b3ff9573
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x86jit: Fix spill issue.
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2023-08-21 08:23:58 -07:00 |
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Henrik Rydgård
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1e269c1d3c
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Merge pull request #17943 from unknownbrackets/x86-ir
Add an x86/x64 backend for IR
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2023-08-21 09:21:37 +02:00 |
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Unknown W. Brackets
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538832940a
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x86jit: Implement some shifts.
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2023-08-21 00:07:42 -07:00 |
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Henrik Rydgård
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61bf366d30
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Merge pull request #17942 from unknownbrackets/irjit-clobber
irjit: Fix regalloc clobber on exit
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2023-08-21 08:04:50 +02:00 |
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Unknown W. Brackets
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2b914046ff
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x86jit: Implement most exits.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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104b6d8c15
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x86jit: Implement some basic arithmetic.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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5045cf012e
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x86jit: Fix flushing of zero register.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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08ea31f405
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x86jit: Improve debug disasm.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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4e7f8cf213
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x86jit: Implement load/store.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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a47b4424e5
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x86jit: Fix some silly mistakes.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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4e3f3860f9
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x86jit: Stub out op categories to files.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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622c69dbb9
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x86jit: Expose option to select new IR based jit.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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c491f701ba
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x86jit: Add initial IR-based jit backend.
It works, but pretty slow in some parts with everything stubbed.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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81e24a9fee
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irjit: Fix regalloc clobber on exit.
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2023-08-20 22:12:52 -07:00 |
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Unknown W. Brackets
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8dfc2f04d7
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riscv: Use a single reg for LO/HI.
This is the same optimization we have for arm64, basically.
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2023-08-20 14:49:09 -07:00 |
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Henrik Rydgård
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629d46ef5b
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Merge pull request #17938 from unknownbrackets/riscv-centralize
Centralize IR regcache from RISC-V
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2023-08-20 23:47:02 +02:00 |
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Henrik Rydgård
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6554b3eb75
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Merge pull request #17939 from unknownbrackets/ir-vec-minor
irjit: Implement vtfm 4x4 using dots
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2023-08-20 23:40:04 +02:00 |
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Unknown W. Brackets
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82fb41cba0
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irjit: Implement vtfm 4x4 using dots.
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2023-08-20 13:50:02 -07:00 |
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Unknown W. Brackets
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36b6aa4728
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riscv: Allow GPR "SIMD" without FPR SIMD.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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6a75e6712e
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riscv: Use automapping for special cases too.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a190793ad2
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riscv: Simplify mapping for more instructions.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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cc4bc406d5
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riscv: Cleanup VfpuCtrlToReg meta, use auto-map.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e40ae60029
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riscv: Mark normalized32 after mapping.
It's less confusing to separate it.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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f9bf7de701
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riscv: Use a single reg cache.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e30fb82a64
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riscv: Remove some unused reg funcs.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a23ade8f75
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riscv: Map IR regs based on metadata.
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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32d8f6196f
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irjit: Cut time flushing imm regs.
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2023-08-20 08:59:47 -07:00 |
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Unknown W. Brackets
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552cd88938
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irjit: Skip some work in PurgeTemps.
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2023-08-20 08:59:47 -07:00 |
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Unknown W. Brackets
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57123e8f9e
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irjit: Reserve some arrays that churn.
Improves IR compile time by around 20-30%.
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2023-08-20 08:59:47 -07:00 |
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Henrik Rydgård
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cd1c5beb60
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Merge pull request #17934 from unknownbrackets/riscv-centralize
RISC-V: Centralize IR regcaches
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2023-08-20 14:49:18 +02:00 |
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Henrik Rydgård
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efcd380842
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Merge pull request #17935 from unknownbrackets/ir-long-inst
irjit: Cleanup Write() calls with extra const
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2023-08-20 09:19:48 +02:00 |
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Unknown W. Brackets
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161465ab66
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riscv: Centralize register FlushAll().
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2023-08-19 21:30:03 -07:00 |
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Unknown W. Brackets
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f3d4bd8c11
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riscv: Centralize reg-as-pointer.
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2023-08-19 21:24:36 -07:00 |
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Unknown W. Brackets
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bd1d93ae6f
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irjit: Cleanup Write() calls with extra const.
Some instructions, such as Vec4Blend, are encoded requiring the const
field, and this interface was designed when we used a pool.
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2023-08-19 16:23:42 -07:00 |
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Unknown W. Brackets
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92f7374c89
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riscv: Centralize reg mapping itself.
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2023-08-19 16:15:49 -07:00 |
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Unknown W. Brackets
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83946eeef8
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Core: Reduce log spam on exit.
This doesn't need to be INFO.
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2023-08-19 16:15:49 -07:00 |
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