Henrik Rydgård and Claude Opus 5.5
d9eab0968a
RISC-V JIT: Compile the bit ops and min/max without Zbb
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Without the Zbb extension, clz, rotr, wsbh, wsbw, bitrev, min and max
went to the IR interpreter, and wsbh always did. They're now base ISA
sequences: a branchless binary search for clz, paired shifts for the
rotates and byte swaps, mask-and-shift steps for bitrev, and a
compare-and-branch for min and max. Checked against a model of the
instructions over random inputs, since nothing here runs RISC-V.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-09-24 14:31:22 -06:00
Henrik Rydgård and Claude Fable 5.1
e0f09c55d5
MIPS: INT_MIN / -1 leaves HI at zero, like the hardware
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Every path special-cased the one signed division overflow and set the
remainder to -1. cpu/cpu_alu/cpu_div, recorded on a PSP, says it's 0.
The classic arm64 JIT was the only one that got it right, by not
special-casing it at all.
arm64, RISC-V and LoongArch all produce INT_MIN with remainder 0 natively,
so their fixup blocks go away. x86 has to keep the check (IDIV traps) but
sets HI to 0 now, and so do both interpreters.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com >
2026-09-22 11:02:20 -06:00
Unknown W. Brackets
8dfc2f04d7
riscv: Use a single reg for LO/HI.
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This is the same optimization we have for arm64, basically.
2023-08-20 14:49:09 -07:00
Unknown W. Brackets
6a75e6712e
riscv: Use automapping for special cases too.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
cc4bc406d5
riscv: Cleanup VfpuCtrlToReg meta, use auto-map.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
e40ae60029
riscv: Mark normalized32 after mapping.
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It's less confusing to separate it.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
f9bf7de701
riscv: Use a single reg cache.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
a23ade8f75
riscv: Map IR regs based on metadata.
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Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
718a1b3944
riscv: Centralize MarkDirty flagging.
2023-08-19 16:15:49 -07:00
Unknown W. Brackets
4e41f83ecc
riscv: Centralize IR reg cache metadata checks.
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These are all largely the same between backends.
2023-08-17 23:03:31 -07:00
Unknown W. Brackets
0b4e7d60f9
riscv: Implement ReverseBits in jit.
2023-08-08 23:17:32 -07:00
Unknown W. Brackets
93e3d35f5d
irjit: Move more to IRNativeBackend, split.
2023-08-06 00:16:43 -07:00
Unknown W. Brackets
e34736fbb2
riscv: Reduce norms in Slt/Sltu overlap cases.
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We can skip an SEXT.W in common cases where the dest and src overlap.
2023-07-30 14:19:28 -07:00
Unknown W. Brackets
d1dc346899
riscv: Fix pointer add/sub.
2023-07-30 14:19:28 -07:00
Unknown W. Brackets
70ff18a463
riscv: Implement count leading zeros.
2023-07-30 00:02:10 -07:00
Unknown W. Brackets
e2765db4dc
riscv: Implement division.
2023-07-29 19:02:15 -07:00
Unknown W. Brackets
18c48681a8
riscv: Implement multiply instructions.
2023-07-23 18:01:50 -07:00
Unknown W. Brackets
7f4689e8fa
riscv: Use direct SLI/SLIU instructions.
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Derp, I forgot these existed on RISC-V for a moment.
2023-07-23 18:01:46 -07:00
Unknown W. Brackets
f7f7531500
riscv: Fix min/max normalization.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
92694e765f
riscv: Implement conditional moves.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
2c7da94bd1
riscv: Implement shifts and compares.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
5ed2f0d559
riscv: Implement logic ops.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
94be343591
riscv: Try to keep regs normalized, track.
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Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
d31eded9ba
riscv: Allow dirty pointers, explicitly.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
c2da7d18bb
riscv: Stub out more IR compilation categories.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
05a2789cf4
riscv: Implement some simple assign instructions.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
bf7a6eb2cd
riscv: Add jit for some initial instructions.
2023-07-23 18:01:00 -07:00
