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129 Commits
Author SHA1 Message Date
Henrik RydgårdandClaude Opus 5 029d17edfc IR: fix FpCondFromReg operand slot, and some smaller IR bugs 
FpCondFromReg's meta is "_G", so the register is in src1 - which is where
every native backend, PropagateConstants and ReorderLoadStore read it.
But IRInterpret read it from dest, and Comp_VecDo3 wrote it to dest to
match. The other emitter passes (0, MIPS_REG_ZERO), so both fields are
zero there and the disagreement stayed hidden.

The result was that vsge/vslt, which save fpcond to IRTEMP_0 and restore
it afterwards, restored r0 (always zero) on the native IR JITs instead of
the saved value, losing any c.cond.s result live across them. Fixed both
the emitter and the interpreter to use src1.

Vec4Pack31To8's SSE2 path computed (v >> 24) << 1, which is (v >> 23)
with bit 23 forced to zero - the scalar and NEON paths both do
(v >> 23) & 0xFF. Shift left first instead. The pspautotests inputs all
happen to have bit 23 clear after the clamp, so this wasn't caught.

Also:
- Evaluate() didn't mask constant-folded shift amounts to 5 bits, though
  the neighbouring one-immediate path does.
- ApplyMemoryValidation only invalidated its address-check cache for ops
  with a 'G' destination, while Interpret and CallReplacement can write
  any GPR - both are barriers, so drop the whole cache when we see one.
- ReduceVec4Flush indexed isVec4 with (src2 & 3) instead of (src2 & ~3)
  for Vec4Scale; a missed optimization rather than a miscompile.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-09-19 10:31:33 -06:00
Henrik Rydgård a810597ac0 Implement MMIO for the JIT (by falling back to the interpreter for load/stores from kernel addresses) 
Fixes the VSH in JIT mode (but NOT ir)
 2026-08-25 00:22:40 +02:00
Henrik Rydgård 0b90e42214 IR Interpreter with fastmemory off: Validate alignment of memory accesses 2026-08-18 10:59:08 +02:00
Henrik Rydgård ae14ebb6ac IRWriter: Remove the confusing and inefficient AddConstant 2026-08-15 18:31:20 +02:00
Henrik Rydgård e01ca5b057 Logging API change (refactor) (#19324) 
* Rename LogType to Log

* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.

* Mac/ARM64 buildfix

* Do the same with the hle result log macros

* Rename the log names to mixed case while at it.

* iOS buildfix

* Qt buildfix attempt, ARM32 buildfix
 2024-07-14 14:42:59 +02:00
Henrik Rydgård 5e3abe3def IRInterpreter compiler: Reject all vec2ops where the prefix is unknown 
Fixes #19164

May help #19172
 2024-05-22 23:19:14 +02:00
Henrik Rydgård 5d8a0b3ac7 Merge pull request #18266 from unknownbrackets/ir-vtfm 
irjit: Fix vhtfm instruction
 2023-09-29 09:43:06 +02:00
Unknown W. Brackets c92148ee2c irjit: Fix vhtfm instruction. 2023-09-28 21:16:54 -07:00
Unknown W. Brackets e104a28b71 irjit: Handle VDet. 2023-09-24 23:03:25 -07:00
Unknown W. Brackets c85886c11e irjit: Use enum for rounding modes. 2023-09-01 22:29:24 -07:00
Unknown W. Brackets 35fe15d718 x86jit: Do not use Vec4Dot for vdot.t. 
It was much slower to do so in LittleBigPlanet.
 2023-08-27 12:39:21 -07:00
Unknown W. Brackets 74e5e43fdc jit: Skip known prefix writes. 
If we already know what's in memory and it's default, we can skip
overwriting with default values.  This is common, actually.
 2023-08-22 23:26:31 -07:00
Unknown W. Brackets 82fb41cba0 irjit: Implement vtfm 4x4 using dots. 2023-08-20 13:50:02 -07:00
Unknown W. Brackets bd1d93ae6f irjit: Cleanup Write() calls with extra const. 
Some instructions, such as Vec4Blend, are encoded requiring the const
field, and this interface was designed when we used a pool.
 2023-08-19 16:23:42 -07:00
Henrik Rydgård 1b2cffe632 Address feedback 2023-08-14 11:06:20 +02:00
Henrik Rydgård ff6e118fff Get rid of a lot of ifdefs around presentation mode. Instead, set things dynamically. 2023-08-14 11:02:29 +02:00
Unknown W. Brackets 159b41a0fa irjit: Fuse unaligned svl.q/svr.q together. 
They're almost never used outside paired, which we can do on most
platforms easily.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets 5729de90d2 irjit: Use more partial Vec4s / Vec4Blend. 2023-08-13 18:10:40 -07:00
Unknown W. Brackets 2e6dbab5fa irjit: Add flag to prefer Vec4, use for add/sub. 
This will improve things when using SIMD.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets e0be6858b8 irjit: Implement vcrs.t. 
As used in Jeanne d'Arc.
 2023-08-13 18:10:12 -07:00
Unknown W. Brackets 217a1837ed irjit: Allow typical prefixes in vdiv/vasin/etc. 
Some of these behave strangely, but there are some common usages that work
fine.
 2023-08-13 18:10:07 -07:00
Unknown W. Brackets 23c79f8e7f irjit: Implement vsge/vslt. 
These are not ideal especially for SIMD, but they do work.
Improves performance in Silent Hill on RISC-V by like 20%.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets 5d20f2aabd irjit: Simplify VecDo3. 2023-08-13 10:40:47 -07:00
Henrik Rydgård 2342c4522c Merge pull request #17875 from unknownbrackets/riscv-jit 
RISC-V: Implement a few more ops
 2023-08-09 09:30:15 +02:00
Unknown W. Brackets 28c58c1d24 irjit: Allow more forms of vmidt. 
Mildly worth it.
 2023-08-08 23:17:32 -07:00
Unknown W. Brackets e73c203984 irjit: Fix Vec4Shuffle overlap issue. 2023-08-08 23:00:39 -07:00
Henrik Rydgård e9431d0d1e Merge pull request #17859 from unknownbrackets/irjit-vec4 
irjit: Use Vec4 a bit more
 2023-08-06 23:05:33 +02:00
Unknown W. Brackets 3dc71cff75 irjit: Keep a couple more ops in Vec4. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets 6a1dbd4cde irjit: Allow Vec4 to be used with masks. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets 2b964fd3b0 irjit: Handle more common Vec4 prefix cases. 2023-08-06 13:38:00 -07:00
Unknown W. Brackets 79ca880ac7 irjit: Implement vqmul, add Vec4Blend. 
Should be useful more places.
 2023-08-06 13:38:00 -07:00
Unknown W. Brackets 85ee7c85c1 irjit: Allow masked vneg.q. 2023-08-06 13:38:00 -07:00
Unknown W. Brackets a29a35b91a irjit: Fix mfvc eating prefixes. 
It doesn't and shouldn't, which is why it's marked as not.
 2023-08-06 08:28:25 -07:00
Unknown W. Brackets 5db6b11ef2 irjit: Cleanup self-fmovs. 
These were sometimes getting emitted.
 2023-07-30 14:16:17 -07:00
Unknown W. Brackets e228748449 irjit: Add FCvtScaledSW to safely scale vi2f. 2023-07-29 18:30:15 -07:00
Unknown W. Brackets a5a2671af3 irjit: Implement vf2ix. 
Used in LittleBigPlanet when playing intro movies.
 2023-07-29 18:01:08 -07:00
Unknown W. Brackets d97790e28e irjit: Fix vi2us/vi2s with non-consecutive. 
Vec2ClampToZero and similar assume consecutive.
 2023-03-15 21:30:35 -07:00
Unknown W. Brackets 9cfcbc46e6 Global: Cleanup initialization/pointer checks. 
Cleaning up a lot of cases of uninitialized data, unchecked return values
for failures, and similar.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets a7b7bf7826 Global: Set many read-only params as const. 
This makes what they do and which args to use clearer, if nothing else.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets c085413326 irjit: Consistently check vec4 safety. 
Just to prevent confusion/surprises, this is clearer.
 2022-11-18 19:06:50 -08:00
Unknown W. Brackets ada0674415 irjit: Allow VV2Op SIMD with exact overlap. 
None of these look at other lanes.
 2022-11-18 17:54:58 -08:00
Unknown W. Brackets 2419e5680a irjit: Correct VV2Op SIMD check. 
It's unlikely, but possible, uninitialized data could cause
IsConsecutive4() to return true when n < 4.
 2022-11-18 17:53:53 -08:00
Henrik Rydgård e97d5498c6 Merge pull request #16306 from unknownbrackets/ir-prefixes 
irjit: Correct prefix validation
 2022-10-31 09:11:52 +01:00
Unknown W. Brackets eef29d5e95 irjit: Correct prefix validation. 
Some vcmps, etc. were perfectly valid but were forcing to interp.
This also catches more cases that should go to interp correctly.
 2022-10-30 23:15:54 -07:00
Unknown W. Brackets 56ff555309 irjit: Fix unordered float compares. 2022-10-30 21:12:59 -07:00
Unknown W. Brackets bbdc8a8f98 interp: Correct vscl/vmscl t prefix handling. 
This makes more sense.  Fixes Dissidia 012 issues.
 2022-10-29 22:43:30 -07:00
Unknown W. Brackets 3f997518f3 irjit: Handle vrot overlap more correctly. 
Sine ignores overlap, cosine does not.
 2022-10-29 22:25:25 -07:00
Unknown W. Brackets 90517ace59 irjit: Validate alignment in slow memory mode. 2022-08-21 13:24:10 -07:00
Unknown W. Brackets f32f89dd90 Global: Remove some unused variables. 2021-02-15 11:59:45 -08:00
Unknown W. Brackets 5d60fa0d0d Common: Maintain C++11 support in sign extend. 2021-01-31 08:44:02 -08:00