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45 Commits
Author SHA1 Message Date
Henrik RydgårdandClaude Opus 5.5 ae32477764 Core: Let 16-bit CPU accesses through the depth mirrors see the GE's layout 
With the software renderer, which now stores depth as the GE does, a
16-bit read or write at VRAM's 0x04200000 or 0x04600000 mirror goes to
where the GE's 16-bit or 32-bit color layout puts that depth pixel
(ppsspp-re geprobe exp88: the mirrors are the layout's exact inverse).
Games access depth there with nothing else, so other widths stay plain.

The accessors check the address, then whether the GPU core is the
software renderer (CoreParameter); the hardware renderers keep depth plain
and handle the layout their own way. The renderer keeps the layouts up to
date with the EDRAM address translation. With it, the JITs send 16-bit
loads and stores to the interpreter, and the IR passes don't change a
load's width to or from 16 bits.
The pspautotests that read depth through the mirrors now do so 16 bits
at a time, re-recorded on hardware unchanged.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
 2026-10-08 18:37:23 +02:00
Henrik RydgårdandClaude Opus 5.5 b87533a128 arm64 JIT: Compile ll/sc, and vcmp EN/NN/ES/NS with vs != vt 
ll and sc always went to the interpreter; a few games use them
thousands of times. They now load and store directly with fast memory,
keeping llBit in MIPSState. vcmp's NaN and inf-or-NaN tests only look
at s, so they no longer need vt to be the same register: EN and NN
compare s with itself.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
 2026-09-24 14:31:22 -06:00
Henrik Rydgård a810597ac0 Implement MMIO for the JIT (by falling back to the interpreter for load/stores from kernel addresses) 
Fixes the VSH in JIT mode (but NOT ir)
 2026-08-25 00:22:40 +02:00
Henrik Rydgård b999c51a1a Code cleanup. Don't use gpr.SetRegImm where all we do is write to a scratch register 2026-02-10 19:28:53 +01:00
Unknown W. Brackets df2462b1d9 irjit: Implement ll/sc. 
These occur more than I expected in LittleBigPlanet while loading.
 2023-07-29 17:57:44 -07:00
Unknown W. Brackets 6df939034a Core: Cleanup some sign extensions for clarity. 2023-04-05 17:16:51 -07:00
Henrik Rydgård 1b596ef82b Fix/workaround ARM64 with the MASKED_PSP_MEMORY build flag. 2020-11-03 00:20:16 +01:00
Henrik Rydgård 4c034ce988 Make all the Comp_Cache implementations the same. 
We have the informative comments in the interpreter implementation
anyway.
 2020-10-16 09:13:41 +02:00
Henrik Rydgård c5e0b799d9 Remove category from _assert_msg_ functions. We don't filter these by category anyway. 
Fixes the inconsistency where we _assert_ didn't take a category but
_assert_msg_ did.
 2020-07-19 20:33:25 +02:00
M4xw b9352354c9 Masked PSP Memory support for the AArch64 Dynarec 2019-04-15 12:07:57 +02:00
Henrik Rydgård c80dd44da8 ARM/ARM64: Ignore invalid immediate addresses in delay slots, which may be conditional. 
Should do something in x86's safe mem too, but leaving for later.

Replaces #11824
 2019-02-23 10:15:09 +01:00
Unknown W. Brackets 419c1fbd73 Jit: Respect flags for jit types and features. 
Left some free space for more.
 2019-02-03 14:57:08 -08:00
Unknown W. Brackets eb4b59b530 arm64jit: Enable breakpoints. 
Memory breakpoints not yet really tested.
 2018-06-06 17:31:56 -07:00
Unknown W. Brackets 7d3fac2b4b arm64jit: Fix a case of R() on unmapped. 
But this probably means a game crash anyway...

Attempting to fix #10843.
 2018-03-31 22:34:05 -07:00
Unknown W. Brackets d8d174fa2b arm64jit: Avoid spilling an extra reg for lwl/lwr. 
It's only needed for swl and swr.
 2018-01-01 08:38:10 -08:00
Unknown W. Brackets e7ac672522 arm64jit: Cleanup method names, temp discard. 
This way MapDirtyIn won't accidentally discard temps.
 2017-12-30 07:51:27 -08:00
Unknown W. Brackets 0fc8274ec4 arm64jit: Enable safe memory for lwl/lwr. 2017-12-29 17:30:18 -08:00
Unknown W. Brackets 5177db0f91 arm64jit: Remove unnecessary address masking. 
We use views like on x86_64, so this isn't needed.
 2017-12-28 23:58:30 -08:00
Unknown W. Brackets 1b1e2c773b arm64jit: Jit lwl/lwr with proper temp regs. 
It's possible rt might overlap with w9/w10, so we really need to allocate
these properly.  This locks and spills as necessary.
 2017-12-28 15:54:03 -08:00
Unknown W. Brackets 970326c9e5 arm64jit: Fix and enable imm lwl/lwr. 2017-12-28 14:49:55 -08:00
Unknown W. Brackets 1b792c32e1 arm64jit: Attempt to reuse imms on sw/etc. 
Mostly, this handles the zero case, but it may help in other cases too.
 2017-12-28 12:32:12 -08:00
Unknown W. Brackets 6fd17fb026 arm64jit: Use reg sum for LDR/STR. 
Skips an add, and should be less ops anyway.
 2017-12-28 10:19:55 -08:00
Henrik Rydgård 2cceba41bc Fix JIT bug in ARM64. Fixes #10183 2017-11-24 13:57:27 +01:00
Henrik Rydgård 8fe171253d Disable lwl/lwr on ARM64 JIT again. Seems b9b2656e93 broke things, see #10020 2017-11-08 12:11:55 +01:00
Henrik Rydgård b9b2656e93 More vulkan microoptimizations. Add more profiler scopes. 2017-08-18 13:48:11 +02:00
Henrik Rydgård ed776d8c0b ARM: Delete obsolete comments and check 2017-08-18 13:48:11 +02:00
Henrik Rydgård a769724fd0 Fix old bug breaking "non-fast" memory on ARM64. May help #9477, also see #9488 2017-03-23 16:53:16 +01:00
Florent Castelli 8c3552de74 cmake: Detect features at compile time 
Instead of relying on manually passed down flags from CMake,
we now have ppsspp_config.h file to create the platform defines for us.
This improves support for multiplatform builds (such as iOS).
 2016-10-19 12:31:19 +02:00
Henrik Rydgard 47f68ae3a3 ARM64 store optimization bugfix 2015-07-16 00:25:32 +02:00
Henrik Rydgard ccd77cfb7a ARM64 stores: Use WZR for any zero immediates. 2015-07-15 20:01:36 +02:00
Henrik Rydgard 56f9aaa164 ARM64: Store zeroes using WZR 2015-07-11 23:53:05 +02:00
Henrik Rydgard dc2f6a30fb ARM64: Fix joining of lwl/lwr and swl/swr. "implement" the cache instruction. 2015-07-11 16:25:22 +02:00
Unknown W. Brackets 66adc4e695 jit: Normalize CONDITIONAL_DISABLE formatting. 2015-07-02 20:31:37 -07:00
Unknown W. Brackets fedbe645e0 arm64: Use all immediate compares in safemem. 
Ah, this is better.
 2015-06-27 00:22:09 -07:00
Unknown W. Brackets 3c29ec2051 arm64: Optimize codesize in safemem path a bit. 
Will only be used for scratchpad, I think.
 2015-06-27 00:22:04 -07:00
Unknown W. Brackets fbd4db0fc4 arm64: Add a safemem path. 
This is probably not optimal but at least it works.
 2015-06-27 00:22:04 -07:00
Henrik Rydgard 2c05334d47 ARM64: Fix bug where we didn't save the FP registers correctly in the vertex decoder. 
Also port a few ops from dolphin's ARM64 emitter.
 2015-06-14 12:56:44 +02:00
Henrik Rydgård a897723e6a Separate out jit reading nearby instructions. 
This makes it easier to use an IR for these things, or remove them.
 2015-04-11 00:53:24 -07:00
Henrik Rydgård a8c2d0945a ARM64: lwl: Pass INVALID_REG to be sure SCRATCH1 doesn't get overwritten... 2015-04-06 18:13:41 +02:00
Henrik Rydgård 13c9390c53 ARM64: Emitter fix, disable swl/swr/lwl/lwr again fully 2015-04-06 18:13:38 +02:00
Henrik Rydgard ad3d539451 ARM64: Attempt at lwl/lwr/swl/swr. The first two don't work 2015-04-06 18:13:35 +02:00
Henrik Rydgard ad648baa9c ARM64 regcache: Add support to "pointerify" registers. Use in load/store to cut down instructions. 2015-04-06 18:13:32 +02:00
Henrik Rydgard 34e61ab875 ARM64: More FPU instructions (int<->float convert), minor stuff 2015-04-06 18:13:25 +02:00
Henrik Rydgard d16bd1fd30 ARM64: Port over basic load/store from ARM. Works in FastMem only. 2015-04-06 18:13:10 +02:00
Henrik Rydgard b309c83973 Initial work on ARM64, based on the ARM jit. 2015-04-06 18:13:01 +02:00