Henrik Rydgård and Claude Opus 5.5
f0ab8a0062
IR native backends: Fix ll into $zero, and sc losing its result
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ll into $zero mapped $zero for writing, which asserts. On ARM64 and
x86-64, sc wrote its 0/1 result into rt without marking it dirty, so it
was never stored (RISC-V and LoongArch already did this right).
See docs/cpu-equivalence.md.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-14 00:10:00 +02:00
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7d0f2e43b6
irjit: Fix safety of kernel bit memory addresses.
2023-09-24 10:18:55 -07:00
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85b80bc9e5
arm64jit: Implement load/store in IR.
2023-09-04 00:04:36 -07:00
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9bac755491
x86jit: Avoid pointerify if clobbered.
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For x86, it's not worth it for one.
2023-09-01 22:34:22 -07:00
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8233fdfd91
x86jit: Implement CondStore.
2023-08-28 23:32:49 -07:00
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edcb156897
x86jit: Add Vec4 and Float load/store.
2023-08-22 10:39:46 +02:00
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55654f52b2
x86jit: Fix Store8 on i386.
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Require an 8-bit capable register in mapping.
2023-08-21 21:05:51 -07:00
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1ccc2d5d2f
x86jit: Fix address offsets with memview mask.
2023-08-21 09:03:10 -07:00
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4e7f8cf213
x86jit: Implement load/store.
2023-08-20 22:28:54 -07:00
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4e3f3860f9
x86jit: Stub out op categories to files.
2023-08-20 22:28:54 -07:00
