Henrik Rydgård and Claude Opus 5.5
f0ab8a0062
IR native backends: Fix ll into $zero, and sc losing its result
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ll into $zero mapped $zero for writing, which asserts. On ARM64 and
x86-64, sc wrote its 0/1 result into rt without marking it dirty, so it
was never stored (RISC-V and LoongArch already did this right).
See docs/cpu-equivalence.md.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-14 00:10:00 +02:00
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7d0f2e43b6
irjit: Fix safety of kernel bit memory addresses.
2023-09-24 10:18:55 -07:00
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85b80bc9e5
arm64jit: Implement load/store in IR.
2023-09-04 00:04:36 -07:00
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e40ae60029
riscv: Mark normalized32 after mapping.
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It's less confusing to separate it.
2023-08-20 12:42:11 -07:00
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f9bf7de701
riscv: Use a single reg cache.
2023-08-20 12:42:11 -07:00
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a23ade8f75
riscv: Map IR regs based on metadata.
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Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
2023-08-20 12:42:11 -07:00
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4e41f83ecc
riscv: Centralize IR reg cache metadata checks.
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These are all largely the same between backends.
2023-08-17 23:03:31 -07:00
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7cc6c5fa62
riscv: Fix load error w/o pointerify.
2023-08-13 10:20:28 -07:00
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93e3d35f5d
irjit: Move more to IRNativeBackend, split.
2023-08-06 00:16:43 -07:00
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c24e3ef831
riscv: Implement ll/sc.
2023-07-30 00:45:51 -07:00
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df2462b1d9
irjit: Implement ll/sc.
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These occur more than I expected in LittleBigPlanet while loading.
2023-07-29 17:57:44 -07:00
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4e17c59cc2
riscv: Implement simple vec4 ops via floats.
2023-07-25 20:33:56 -07:00
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bb6fdd0246
riscv: Add floating point load/stores.
2023-07-25 20:33:56 -07:00
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94be343591
riscv: Try to keep regs normalized, track.
...
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
2023-07-23 18:01:00 -07:00
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165169eb31
riscv: Implement load and store ops.
2023-07-23 18:01:00 -07:00
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c2da7d18bb
riscv: Stub out more IR compilation categories.
2023-07-23 18:01:00 -07:00
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bf7a6eb2cd
riscv: Add jit for some initial instructions.
2023-07-23 18:01:00 -07:00
