Henrik Rydgård and Claude Opus 5.5
4849ef020e
Decode the unused bits of shifts and Allegrex bit ops as the PSP does
...
srl/srlv rotate when the low bit of their unused field (rs or sa) is
set and shift when it's clear, whatever the other bits hold
(cpu/cpu_alu/shift_encodings). The interpreter treated values above 1 as
invalid and the other cores shifted.
The Allegrex bit ops decode only some bits of sa, so all 32 values are
one of wsbh, wsbw, seb, seh and bitrev (cpu/cpu_alu/allegrex_encodings).
AllegrexBitOp() gives the canonical one for every core. Special3
function 0x18 does nothing on the PSP, where it was decoded as an alias
of 0x20.
The interpreter dispatch is regenerated, and its generator now lists
each instruction name once. CPUEquivalence no longer skips the srl/srlv
encodings.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
2026-10-14 10:56:48 +02:00
Henrik Rydgård
ae14ebb6ac
IRWriter: Remove the confusing and inefficient AddConstant
2026-08-15 18:31:20 +02:00
Henrik Rydgård
982a83d867
IRInterpreter: Optimize variable shifts (no need to mask by 0x1f)
2024-06-24 09:30:21 +02:00
Henrik Rydgård
2ff91fab2b
Optimize a common case of the ins instruction
2024-06-08 23:10:29 +02:00
Unknown W. Brackets
56ff555309
irjit: Fix unordered float compares.
2022-10-30 21:12:59 -07:00
Unknown W. Brackets
5d60fa0d0d
Common: Maintain C++11 support in sign extend.
2021-01-31 08:44:02 -08:00
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1b00da2f3a
Common: Sign extend w/func not chained casts.
...
Should be clearer to read and easier to get right.
2021-01-31 01:25:52 -08:00
Unknown W. Brackets
d3c06266c5
jit: Fix conditional disable flags.
2021-01-09 11:50:32 -08:00
Unknown W. Brackets
419c1fbd73
Jit: Respect flags for jit types and features.
...
Left some free space for more.
2019-02-03 14:57:08 -08:00
Henrik Rydgård
fb0e81484b
Minor cleanup
2018-01-10 09:19:27 +01:00
Unknown W. Brackets
905d2c2da6
irjit: Cleanup some invalid op handling.
...
And log blocks the same way as other backends.
2018-01-01 08:38:11 -08:00
Unknown W. Brackets
c606f64f71
jit-ir: Add div/divu instructions.
2016-05-14 19:23:52 -07:00
Unknown W. Brackets
6413b44434
jit-ir: Enable IR for madd(u)/msub(u).
2016-05-14 19:23:51 -07:00
Unknown W. Brackets
a05ae2a0a6
Correct divide by zero HI/LO values a bit.
...
Interpreter is now correct, but it's probably not all that important to
get right in jit.
2016-05-14 19:23:50 -07:00
Unknown W. Brackets
4ac773e8b4
jit-ir: Implement bit reverse instruction.
2016-05-14 18:21:42 -07:00
Henrik Rydgard
558bb197c7
More VFPU
2016-05-09 23:47:56 +02:00
Henrik Rydgard
e806c369b2
Separate the IR frontend from the IR "Jit"
2016-05-09 19:57:18 +02:00
Unknown W. Brackets
5221a02db4
jit-ir: Propagate constants for shifts.
...
This might optimize away an IRTEMP_0 in such cases.
2016-05-08 19:11:58 -07:00
Henrik Rydgard
492ea5fac4
Address a bunch of comments, thanks for the review
2016-05-08 21:38:03 +02:00
Henrik Rydgard
14df39d7c9
Fix IRTEMP clash bug. Add more cases to the constant propagation pass.
2016-05-08 10:36:37 +02:00
Henrik Rydgard
aae32bd929
ir-jit: Re-enable mult. Fix bvf/bvt
2016-05-08 02:47:19 +02:00
Henrik Rydgard
e750987052
ir-jit: Fix bug in ext
2016-05-08 02:09:01 +02:00
Henrik Rydgard
7d4774db4c
Fix wsbw
2016-05-08 02:08:25 +02:00
Henrik Rydgard
09969c0156
Use the regcache in a new (incomplete) pass, PropagateConstants.
2016-05-08 01:06:07 +02:00
Henrik Rydgard
a33f8b68c6
ir-jit: Get rid of the regcache. Should be replaced with optimization passes.
2016-05-07 23:12:53 +02:00
Henrik Rydgard
750d520cc7
Initial work on mult and friends. Fix another bug.
2016-05-07 22:27:58 +02:00
Henrik Rydgard
12edfcea5a
Enough to run cpu_alu.prx.
2016-05-07 21:00:30 +02:00
Henrik Rydgard
4acf85aa06
It's kind of starting to run
2016-05-07 17:37:19 +02:00
Henrik Rydgard
d399c4a470
Initial commit for IRJit
2016-05-07 13:58:29 +02:00
