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https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
4849ef020e
srl/srlv rotate when the low bit of their unused field (rs or sa) is set and shift when it's clear, whatever the other bits hold (cpu/cpu_alu/shift_encodings). The interpreter treated values above 1 as invalid and the other cores shifted. The Allegrex bit ops decode only some bits of sa, so all 32 values are one of wsbh, wsbw, seb, seh and bitrev (cpu/cpu_alu/allegrex_encodings). AllegrexBitOp() gives the canonical one for every core. Special3 function 0x18 does nothing on the PSP, where it was decoded as an alias of 0x20. The interpreter dispatch is regenerated, and its generator now lists each instruction name once. CPUEquivalence no longer skips the srl/srlv encodings. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
401 lines
9.1 KiB
C++
401 lines
9.1 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include <algorithm>
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/IR/IRFrontend.h"
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#include "Common/CPUDetect.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE(flag) { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE(flag) if (opts.disableFlags & (uint32_t)JitDisable::flag) { Comp_Generic(op); return; }
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#define DISABLE { Comp_Generic(op); return; }
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#define INVALIDOP { Comp_Generic(op); return; }
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namespace MIPSComp {
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void IRFrontend::Comp_IType(MIPSOpcode op) {
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CONDITIONAL_DISABLE(ALU_IMM);
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u32 uimm = (u16)_IMM16;
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s32 simm = SignExtend16ToS32(op);
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u32 suimm = SignExtend16ToU32(op);
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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// noop, won't write to ZERO.
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if (rt == MIPS_REG_ZERO)
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return;
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switch (op >> 26) {
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case 8: // same as addiu?
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case 9: // R(rt) = R(rs) + simm; break; //addiu
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ir.Write(IROp::AddConst, rt, rs, 0, (u32)simm);
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break;
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case 12: ir.Write(IROp::AndConst, rt, rs, 0, uimm); break;
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case 13: ir.Write(IROp::OrConst, rt, rs, 0, uimm); break;
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case 14: ir.Write(IROp::XorConst, rt, rs, 0, uimm); break;
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case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
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ir.Write(IROp::SltConst, rt, rs, 0, (u32)simm);
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break;
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case 11: // R(rt) = R(rs) < suimm; break; //sltiu
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ir.Write(IROp::SltUConst, rt, rs, 0, suimm);
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break;
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case 15: // R(rt) = uimm << 16; //lui
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ir.WriteSetConstant(rt, uimm << 16);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void IRFrontend::Comp_RType2(MIPSOpcode op) {
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CONDITIONAL_DISABLE(ALU_BIT);
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MIPSGPReg rs = _RS;
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MIPSGPReg rd = _RD;
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// Don't change $zr.
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if (rd == MIPS_REG_ZERO)
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return;
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switch (op & 63) {
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case 22: //clz
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ir.Write(IROp::Clz, rd, rs);
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break;
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case 23: //clo
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ir.Write(IROp::Not, IRTEMP_0, rs);
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ir.Write(IROp::Clz, rd, IRTEMP_0);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void IRFrontend::Comp_RType3(MIPSOpcode op) {
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CONDITIONAL_DISABLE(ALU);
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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MIPSGPReg rd = _RD;
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// noop, won't write to ZERO.
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if (rd == MIPS_REG_ZERO)
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return;
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switch (op & 63) {
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case 10: //if (!R(rt)) R(rd) = R(rs); break; //movz
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ir.Write(IROp::MovZ, rd, rt, rs);
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break;
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case 11:// if (R(rt)) R(rd) = R(rs); break; //movn
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ir.Write(IROp::MovNZ, rd, rt, rs);
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break;
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case 32: //R(rd) = R(rs) + R(rt); break; //add
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case 33: //R(rd) = R(rs) + R(rt); break; //addu
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ir.Write(IROp::Add, rd, rs, rt);
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break;
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case 34: //R(rd) = R(rs) - R(rt); break; //sub
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case 35: //R(rd) = R(rs) - R(rt); break; //subu
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ir.Write(IROp::Sub, rd, rs, rt);
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break;
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case 36: //R(rd) = R(rs) & R(rt); break; //and
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ir.Write(IROp::And, rd, rs, rt);
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break;
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case 37: //R(rd) = R(rs) | R(rt); break; //or
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ir.Write(IROp::Or, rd, rs, rt);
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break;
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case 38: //R(rd) = R(rs) ^ R(rt); break; //xor/eor
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ir.Write(IROp::Xor, rd, rs, rt);
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break;
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case 39: // R(rd) = ~(R(rs) | R(rt)); break; //nor
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if (rs == 0) {
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ir.Write(IROp::Not, rd, rt);
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} else if (rt == 0) {
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ir.Write(IROp::Not, rd, rs);
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} else {
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ir.Write(IROp::Or, IRTEMP_0, rs, rt);
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ir.Write(IROp::Not, rd, IRTEMP_0);
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}
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break;
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case 42: //R(rd) = (int)R(rs) < (int)R(rt); break; //slt
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ir.Write(IROp::Slt, rd, rs, rt);
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break;
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case 43: //R(rd) = R(rs) < R(rt); break; //sltu
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ir.Write(IROp::SltU, rd, rs, rt);
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break;
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case 44: //R(rd) = max(R(rs), R(rt); break; //max
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ir.Write(IROp::Max, rd, rs, rt);
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break;
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case 45: //R(rd) = min(R(rs), R(rt)); break; //min
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ir.Write(IROp::Min, rd, rs, rt);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void IRFrontend::CompShiftImm(MIPSOpcode op, IROp shiftOpImm, int sa) {
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MIPSGPReg rd = _RD;
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MIPSGPReg rt = _RT;
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ir.Write(shiftOpImm, rd, rt, sa);
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}
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void IRFrontend::CompShiftVar(MIPSOpcode op, IROp shiftOp) {
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MIPSGPReg rd = _RD;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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if (opts.optimizeForInterpreter) {
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// The interpreter already masks where needed, don't need to generate extra ops.
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ir.Write(shiftOp, rd, rt, rs);
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} else {
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ir.Write(IROp::AndConst, IRTEMP_0, rs, 0, (u32)31);
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ir.Write(shiftOp, rd, rt, IRTEMP_0);
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}
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}
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void IRFrontend::Comp_ShiftType(MIPSOpcode op) {
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CONDITIONAL_DISABLE(ALU);
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MIPSGPReg rs = _RS;
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MIPSGPReg rd = _RD;
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int sa = _SA;
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// noop, won't write to ZERO.
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if (rd == MIPS_REG_ZERO)
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return;
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// WARNING: srl/rotr and srlv/rotrv share encodings, told apart by the low bit of the unused field.
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switch (op & 0x3f) {
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case 0: CompShiftImm(op, IROp::ShlImm, sa); break; //sll
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case 2: CompShiftImm(op, ((rs & 1) ? IROp::RorImm : IROp::ShrImm), sa); break; //srl
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case 3: CompShiftImm(op, IROp::SarImm, sa); break; //sra
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case 4: CompShiftVar(op, IROp::Shl); break; //sllv
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case 6: CompShiftVar(op, ((sa & 1) ? IROp::Ror : IROp::Shr)); break; //srlv
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case 7: CompShiftVar(op, IROp::Sar); break; //srav
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default:
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INVALIDOP;
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break;
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}
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}
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void IRFrontend::Comp_Special3(MIPSOpcode op) {
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CONDITIONAL_DISABLE(ALU_BIT);
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MIPSGPReg rs = _RS;
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MIPSGPReg rt = _RT;
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int pos = _POS;
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int size = _SIZE + 1;
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u32 mask = 0xFFFFFFFFUL >> (32 - size);
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// Don't change $zr.
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if (rt == MIPS_REG_ZERO)
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return;
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switch (op & 0x3f) {
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case 0x0: // ext
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if (pos != 0) {
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ir.Write(IROp::ShrImm, rt, rs, pos);
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ir.Write(IROp::AndConst, rt, rt, 0, mask);
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} else {
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ir.Write(IROp::AndConst, rt, rs, 0, mask);
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}
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break;
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case 0x4: //ins
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{
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// TODO: Might be good to support natively in the interpreter. Though, would have to
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// abuse a register as a constant
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u32 sourcemask = mask >> pos;
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u32 destmask = ~(sourcemask << pos);
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if (size != 32) {
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// Need to use the sourcemask.
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ir.Write(IROp::AndConst, IRTEMP_0, rs, 0, sourcemask);
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if (pos != 0) {
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ir.Write(IROp::ShlImm, IRTEMP_0, IRTEMP_0, pos);
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}
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} else {
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// If the shl takes care of the sourcemask, don't need to and.
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if (pos != 0) {
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ir.Write(IROp::ShlImm, IRTEMP_0, rs, pos);
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} else {
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ir.Write(IROp::Mov, IRTEMP_0, rs);
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}
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}
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ir.Write(IROp::AndConst, rt, rt, 0, destmask);
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ir.Write(IROp::Or, rt, rt, IRTEMP_0);
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void IRFrontend::Comp_Allegrex(MIPSOpcode op) {
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CONDITIONAL_DISABLE(ALU_BIT);
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MIPSGPReg rt = _RT;
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MIPSGPReg rd = _RD;
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// Don't change $zr.
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if (rd == MIPS_REG_ZERO)
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return;
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switch (AllegrexBitOp(op)) {
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case 16: // seb // R(rd) = SignExtend8ToU32(R(rt));
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ir.Write(IROp::Ext8to32, rd, rt);
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break;
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case 24: // seh
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ir.Write(IROp::Ext16to32, rd, rt);
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break;
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case 20: // bitrev
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ir.Write(IROp::ReverseBits, rd, rt);
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break;
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default:
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INVALIDOP;
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return;
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}
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}
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void IRFrontend::Comp_Allegrex2(MIPSOpcode op) {
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CONDITIONAL_DISABLE(ALU_BIT);
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MIPSGPReg rt = _RT;
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MIPSGPReg rd = _RD;
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// Don't change $zr.
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if (rd == MIPS_REG_ZERO)
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return;
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switch (AllegrexBitOp(op)) {
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case 2: //wsbh
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ir.Write(IROp::BSwap16, rd, rt);
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break;
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case 3: //wsbw
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ir.Write(IROp::BSwap32, rd, rt);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void IRFrontend::Comp_MulDivType(MIPSOpcode op) {
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CONDITIONAL_DISABLE(MULDIV);
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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MIPSGPReg rd = _RD;
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switch (op & 63) {
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case 16: // R(rd) = HI; //mfhi
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if (rd != MIPS_REG_ZERO) {
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ir.Write(IROp::MfHi, rd);
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}
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break;
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case 17: // HI = R(rs); //mthi
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ir.Write(IROp::MtHi, 0, rs);
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break;
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case 18: // R(rd) = LO; break; //mflo
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if (rd != MIPS_REG_ZERO) {
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ir.Write(IROp::MfLo, rd);
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}
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break;
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case 19: // LO = R(rs); break; //mtlo
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ir.Write(IROp::MtLo, 0, rs);
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break;
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case 24: //mult (the most popular one). lo,hi = signed mul (rs * rt)
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ir.Write(IROp::Mult, 0, rs, rt);
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break;
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case 25: //multu (2nd) lo,hi = unsigned mul (rs * rt)
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ir.Write(IROp::MultU, 0, rs, rt);
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break;
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case 26: //div
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ir.Write(IROp::Div, 0, rs, rt);
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break;
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case 27: //divu
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ir.Write(IROp::DivU, 0, rs, rt);
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break;
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case 28: //madd
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ir.Write(IROp::Madd, 0, rs, rt);
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break;
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case 29: //maddu
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ir.Write(IROp::MaddU, 0, rs, rt);
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break;
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case 46: // msub
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ir.Write(IROp::Msub, 0, rs, rt);
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break;
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case 47: // msubu
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ir.Write(IROp::MsubU, 0, rs, rt);
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break;
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default:
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INVALIDOP;
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}
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}
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}
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