preserve-emulation/ppsspp
1
0 Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2026-11-14 10:09:32 +01:00
Code Issues Packages Projects Releases Wiki Activity
26,441 Commits 86 Branches 131 Tags
50d7d64eaa021c8b076d397468b0294a4dca1663
Commit Graph
227 Commits
Author SHA1 Message Date
Henrik Rydgård f65a71d6d8 Compat: Option to use accurate dotprod for VMMUL. 
Eliminates Tekken 6 leg shaking.
 2019-08-05 11:44:52 -07:00
Henrik Rydgård f49999efca Revert "ARM64 vmmul experiment: Disable if S and T matrices overlap." 
This reverts commit c4d26dcb10.
 2019-06-06 09:34:23 +02:00
Henrik Rydgård 649b7a5671 ARM64 vmmov experiment: Reduce precision by using FMUL+FADD instead of FMADD. May help #12082 and thus also #11179 and #9843. 2019-06-05 00:02:32 +02:00
Henrik Rydgård c4d26dcb10 ARM64 vmmul experiment: Disable if S and T matrices overlap. 
If this fixes anything in #12082, we have a regalloc bug I guess...
 2019-06-04 22:24:19 +02:00
Henrik Rydgård 7853c90abb JIT: Split VFPU_MTX disable options. To help with #9843 2019-06-03 23:28:15 +02:00
Unknown W. Brackets c773359095 arm64jit: Tweak matrix vfpu overlap detect, etc. 
Tried making changes to them to guess at issues for #9843, but didn't find
any.  Still, I think these changes are worthwhile, if small.
 2019-06-02 22:10:20 -07:00
Unknown W. Brackets 1358a80aa6 arm64jit: Fix avoidLoad handling for fpu regs. 2019-06-02 22:03:06 -07:00
Henrik Rydgård 55b4b4b9e3 Style fix 2019-06-02 16:22:19 +02:00
Henrik Rydgård 6fd40332fd JitDisable: Add option to disable regalloc across instructions (flush after every instruction) 2019-06-02 16:06:10 +02:00
M4xw b9352354c9 Masked PSP Memory support for the AArch64 Dynarec 2019-04-15 12:07:57 +02:00
Unknown W. Brackets a5214d0b1a Jit: Ignore high bit in vmfvc/vmtvc. 2019-03-31 17:09:55 -07:00
Unknown W. Brackets 5749ae09d0 interp: Correct vmfvc register behavior. 
The target and source registers were completely wrong.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets d5273f589a interp: Mask value in vpfxd. 
The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
 2019-03-31 08:23:36 -07:00
Unknown W. Brackets 6178a1fb33 Jit: Correct vocp prefix handling. 
See #5549.  Matches tests for various prefix settings.
 2019-02-23 09:15:26 -08:00
Henrik Rydgård c80dd44da8 ARM/ARM64: Ignore invalid immediate addresses in delay slots, which may be conditional. 
Should do something in x86's safe mem too, but leaving for later.

Replaces #11824
 2019-02-23 10:15:09 +01:00
Unknown W. Brackets d7f40afd9d interp: Correct vocp prefix handling. 
Also, guess that vsocp also applies prefixes.  See #5549.
 2019-02-21 19:02:16 -08:00
Unknown W. Brackets 419c1fbd73 Jit: Respect flags for jit types and features. 
Left some free space for more.
 2019-02-03 14:57:08 -08:00
Unknown W. Brackets 4c3fe47372 jit: Remove unused breakpoint code. 2018-06-06 17:31:56 -07:00
Unknown W. Brackets eb4b59b530 arm64jit: Enable breakpoints. 
Memory breakpoints not yet really tested.
 2018-06-06 17:31:56 -07:00
Unknown W. Brackets 4861cadb79 arm64jit: Fix reg size in jr delay slot path. 
Can't use the 64-bit reg.
 2018-04-04 06:58:12 -07:00
Unknown W. Brackets ab809bd19e jit: Apply hasSetRounding at compile time. 
Otherwise, the block will be executed with the wrong rounding mode the
first time rounding is set.  This could be important if it was set for a
single operation.

This is only a problem the first time it's set.
 2018-04-01 10:36:16 -07:00
Unknown W. Brackets 09e307b097 arm64jit: Update rounding mode on thread switch. 
Since fcr31 is per-thread, we must update jit state when it changes.
This also fixes the rounding mode on load state and jit/interp switch.
 2018-04-01 10:12:32 -07:00
Unknown W. Brackets 7d3fac2b4b arm64jit: Fix a case of R() on unmapped. 
But this probably means a game crash anyway...

Attempting to fix #10843.
 2018-03-31 22:34:05 -07:00
Unknown W. Brackets 4fbb68d505 arm64jit: Update some comments. 2018-03-31 21:03:23 -07:00
Henrik Rydgård 468b830bec Show IR disassembly in JIT Compare screen 2018-01-04 12:23:23 +01:00
Unknown W. Brackets d8d174fa2b arm64jit: Avoid spilling an extra reg for lwl/lwr. 
It's only needed for swl and swr.
 2018-01-01 08:38:10 -08:00
Unknown W. Brackets 8ffb0101fe jit: Report blocks with uneaten VFPU prefixes. 
There may be options to avoid, like continuing these blocks, especially if
they're likely or something.
 2018-01-01 08:38:10 -08:00
Unknown W. Brackets 9ff812b313 arm64jit: Negate in ADDI2R/SUBI2R as well. 
Should've done this at the same time as CMN.  It's not as common, mostly
catches addu calls, but it's good to have these generic for other uses.
 2017-12-30 11:11:04 -08:00
Unknown W. Brackets ae63628360 arm64jit: Statically allocate ra as well. 
This doesn't seem to have a significant impact on performance, but it
improves bloat by about 5%.
 2017-12-30 11:11:03 -08:00
Unknown W. Brackets 89cbf36611 arm64jit: Free up W23 for static alloc. 
We shouldn't always reserve W23 for this uncommon case.
 2017-12-30 07:51:27 -08:00
Unknown W. Brackets e7ac672522 arm64jit: Cleanup method names, temp discard. 
This way MapDirtyIn won't accidentally discard temps.
 2017-12-30 07:51:27 -08:00
Unknown W. Brackets 0fc8274ec4 arm64jit: Enable safe memory for lwl/lwr. 2017-12-29 17:30:18 -08:00
Unknown W. Brackets c00044c5d8 arm64jit: Avoid arithmetic movs. 
ORR is the preferred encoding and may be faster on some chips.
 2017-12-29 17:30:18 -08:00
Unknown W. Brackets 98ed6fab3f arm64jit: Fix spilling for more than one temp reg. 
Otherwise we hang trying to spill the same reg over and over.
 2017-12-29 17:30:17 -08:00
Unknown W. Brackets ee236743f0 arm64jit: Use TBZ/TBNZ for vfpu branch as well. 2017-12-29 17:30:16 -08:00
Unknown W. Brackets 3b4917a308 arm64jit: Use TBZ/TBNZ for fp branches. 2017-12-29 17:30:15 -08:00
Unknown W. Brackets c71285c970 arm64jit: Use CBZ/CBNZ for zero compare branches. 
These are pretty common, so it reduces bloat decently.  Seems about the
same speed, though.
 2017-12-29 17:30:15 -08:00
Unknown W. Brackets 7f8a871e30 arm64jit: Handle more imm compare cases. 2017-12-29 17:30:14 -08:00
Unknown W. Brackets 56d64f5c67 arm64jit: Avoid temporary on variable shift. 
I think we should trust that it works per the spec.
 2017-12-29 17:30:12 -08:00
Unknown W. Brackets 1ecce2a2e1 arm64jit: Reuse code in I2R funcs. 2017-12-29 17:30:07 -08:00
Unknown W. Brackets 2498ce5e3e arm64jit: Oops, properly init temp locked flag. 
Fixes #10469.
 2017-12-29 14:36:18 -08:00
Unknown W. Brackets 5177db0f91 arm64jit: Remove unnecessary address masking. 
We use views like on x86_64, so this isn't needed.
 2017-12-28 23:58:30 -08:00
Unknown W. Brackets 27116dcb86 arm64jit: Avoid flushing when mapping as pointer. 2017-12-28 16:04:34 -08:00
Unknown W. Brackets 1b1e2c773b arm64jit: Jit lwl/lwr with proper temp regs. 
It's possible rt might overlap with w9/w10, so we really need to allocate
these properly.  This locks and spills as necessary.
 2017-12-28 15:54:03 -08:00
Unknown W. Brackets 970326c9e5 arm64jit: Fix and enable imm lwl/lwr. 2017-12-28 14:49:55 -08:00
Unknown W. Brackets 1b792c32e1 arm64jit: Attempt to reuse imms on sw/etc. 
Mostly, this handles the zero case, but it may help in other cases too.
 2017-12-28 12:32:12 -08:00
Unknown W. Brackets 08e85d0cd4 arm64jit: Autodetect pointerify support. 
Also, re-enable static alloc without pointerify, it works now.
 2017-12-28 10:48:55 -08:00
Unknown W. Brackets 2e1d85a55b arm64jit: Allow reg ptr offsets when unaligned. 
Since now they support being dirty.
 2017-12-28 10:45:50 -08:00
Unknown W. Brackets c4c28282cf arm64jit: Allow ARMREG_AS_PTR to be dirty. 
Since we can just add/sub, then it should be valid (as long as we only
offset it when dirty.)
 2017-12-28 10:40:31 -08:00
Unknown W. Brackets 6fd17fb026 arm64jit: Use reg sum for LDR/STR. 
Skips an add, and should be less ops anyway.
 2017-12-28 10:19:55 -08:00