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Author SHA1 Message Date
Henrik Rydgård ce45c943be Bump naett with fix for build problem on newer NDK 
See #17583
 2023-07-26 07:28:25 +02:00
Unknown W. Brackets 5122b0c78e riscv: Cleanup unnecessary fcr31 func. 
Don't need this, we use DYNAMIC.
 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 0c9dce8ba8 riscv: Implement vec4 dot. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 23e9dffc68 riscv: Implement vec4 shuffle and init. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 4e17c59cc2 riscv: Implement simple vec4 ops via floats. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets df313bd296 riscv: Fix rounding mode setting. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 9157d992ac jit-ir: Implement cfc1/ctc1. 
This makes it so we can track rounding mode changes.
 2023-07-25 20:33:56 -07:00
Unknown W. Brackets ca7a520a19 riscv: Implement FMul. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 9a9b371856 riscv: Implement FSign using FCLASS. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 05360d5c7a riscv: Implement simplest float ops. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets bb6fdd0246 riscv: Add floating point load/stores. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 7071884a47 riscv: Handle rounding mode and ctrl transfers. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 067a033dc0 riscv: Add FPU regcache. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets c3db3d5187 arm64jit: When rouding unset, use nearest. 
The 0/default rounding mode is nearest, not toward zero.
We set hasSetRounding only when fcr31 has a non-zero rounding mode or
flush to zero set.
 2023-07-25 20:30:05 -07:00
Unknown W. Brackets 94f7231e73 net: Fix request cancelling. 
Was broken in #17737.
 2023-07-25 19:42:37 -07:00
Unknown W. Brackets 8f404a1961 softgpu: Fix minor typo. 2023-07-25 19:42:36 -07:00
Unknown W. Brackets a8edf5fa24 riscv: Reduce bloat in jit fallbacks. 2023-07-25 19:42:04 -07:00
Unknown W. Brackets b97b7f3663 riscv: Make some regcache methods private. 2023-07-25 19:42:04 -07:00
Henrik Rydgård f229573bb2 Merge pull request #16251 from gucio321/fix-wayland-vulkan 
CMakeList: fix SDL+Wayland+Vulkan
 2023-07-25 09:52:43 +02:00
Unknown W. Brackets 3383d5b93a Merge pull request #17751 from unknownbrackets/riscv-jit 
Initial RISC-V jit based on IR
 2023-07-25 00:42:22 -07:00
Hoe Hao Cheng 2b826b5614 SDL: implement TextDrawer using SDL2_ttf 2023-07-25 13:05:32 +08:00
Henrik Rydgård f3c89e49f0 Merge pull request #17778 from hrydgard/new-icons 
Add some new UI icons
 2023-07-24 15:49:38 +02:00
Henrik Rydgård fecd0b8cd7 Use the new play button icon in the retroachievement sound customizer 2023-07-24 14:56:35 +02:00
Henrik Rydgård 2baba83f1a Add a bunch of new icon images to the atlas. 2023-07-24 14:52:32 +02:00
Henrik Rydgård 3c2f67a097 Merge pull request #17777 from hrydgard/fix-achievements-from-frontend 
RetroAchievements: Fix another race condition, improve logging.
 2023-07-24 12:37:40 +02:00
Henrik Rydgård a72c4aa383 Actually fix the race condition. Can't do any initialization step while waiting. 2023-07-24 12:08:15 +02:00
Henrik Rydgård 3ae520c35d RetroAchievements: Fix another race condition, improve logging. 
Seems to help the frontend problem.
 2023-07-24 12:00:16 +02:00
Henrik Rydgård bee2400230 Merge pull request #17769 from unknownbrackets/vertexjit-debug 
Add compilation-enabled vertexjit compare tool
 2023-07-24 09:39:52 +02:00
Henrik Rydgård c697dca3e0 Merge pull request #17776 from unknownbrackets/riscv-vertexjit 
Correct a few more RISC-V vertexjit bugs
 2023-07-24 09:13:17 +02:00
Unknown W. Brackets b6f83ca969 riscv: Cleanup some pointerification flags. 2023-07-23 21:17:55 -07:00
Unknown W. Brackets 18c48681a8 riscv: Implement multiply instructions. 2023-07-23 18:01:50 -07:00
Unknown W. Brackets 7f4689e8fa riscv: Use direct SLI/SLIU instructions. 
Derp, I forgot these existed on RISC-V for a moment.
 2023-07-23 18:01:46 -07:00
Unknown W. Brackets ca15fa7061 riscv: Enable jit by default. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 4100767b5e riscv: Optimize SetConst a bit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets f7f7531500 riscv: Fix min/max normalization. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 34bfe93ea5 riscv: Fix block lookup issues. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 92694e765f riscv: Implement conditional moves. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 2c7da94bd1 riscv: Implement shifts and compares. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 5ed2f0d559 riscv: Implement logic ops. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 94be343591 riscv: Try to keep regs normalized, track. 
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 7aafa11d24 riscv: Implement conditional exits. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 8ee73264bf riscv: Correct depointerify on FlushAll(). 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 720f868a10 riscv: Use R_RA as a temporary for calls. 
This is the most logical thing, since we're about to write it anyway.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 76e3246065 riscv: Reduce jit codesize a bit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets d31eded9ba riscv: Allow dirty pointers, explicitly. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 624caa2dea riscv: Implement the simplest exits. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 1dfedde741 riscv: Avoid needless save/load around compile. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 165169eb31 riscv: Implement load and store ops. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets c2da7d18bb riscv: Stub out more IR compilation categories. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 05a2789cf4 riscv: Implement some simple assign instructions. 2023-07-23 18:01:00 -07:00