Commit Graph
158 Commits
Author SHA1 Message Date
Henrik Rydgård 67ddf899ba Plumb through the PC value for syscalls, so we can get better diagnostics for unresolved ones. 2026-08-15 19:14:13 +02:00
Henrik Rydgård eb0813c0e3 Add a utility function for all the ABIs to call functions with a pointer arg. Use to call Advance from the JIT with the MIPSContext. Indent some code better. 2026-08-13 08:09:30 +02:00
Henrik RydgårdandClaude Sonnet 5 ffad0acea1 Plumb an explicit MIPSState *mips through the interpreter's Int_* handlers
All ~82 MIPSInt::Int_* functions (Interpreter.cpp/.h,
InterpreterVFPU.cpp/.h) now take an explicit MIPSState *mips instead
of reaching for the global currentMIPS internally, along with their
file-local helpers (DelayBranchTo, SkipLikely, ApplySwizzleS/T,
ApplyPrefixD/ST, RetainInvalidSwizzleST, EatPrefixes). MIPSInterpretFunc,
Interpret(), ExecInstruction()/InterpreterDispatch.cpp (regenerated),
and RunUntilFast() all thread mips through accordingly.

Deliberately left on currentMIPS for now: MIPSVFPUUtils.cpp's
ReadVector/WriteVector/ReadMatrix/WriteMatrix/VFPURewritePrefix -
these are shared with every JIT backend's compile-time VFPU code, so
parameterizing them would balloon this into a JIT-wide refactor. This
is a partial refactor; that's the next boundary to push on.

Several JIT backends (x86 Jit.cpp, ARM/ArmJit.cpp, ARM64/Arm64Jit.cpp,
x86/X64IRJit.cpp, RiscV/RiscVJit.cpp, LoongArch64/LoongArch64Jit.cpp,
ARM64/Arm64IRJit.cpp) bake the raw interpreter function pointer
directly into JIT-generated machine code as their "fall back to the
interpreter for this one op" mechanism, with only a single argument
register set up for the call. Rather than hand-editing register
allocation across four architectures that can't be build-tested here,
added MIPSInterpretTrampoline(MIPSOpcode op) - a 1-arg wrapper around
MIPSInterpret(currentMIPS, op) - and pointed all 7 such call sites at
it instead, leaving that codegen untouched. Two other call sites
(JitLogMiss, JitBranchLog) were plain C++ calls and just got the
extra argument directly.

Verified (Windows x64): PPSSPPWindows/PPSSPPHeadless/UnitTest all
build clean, 49/49 unit tests pass. `test.py -g --graphics=software`:
interpreter 312/314 (cpu/fpu/fpu is the pre-existing, unrelated
interpreter-vs-JIT denormal difference; gpu/rendertarget/copy passes
standalone, so was cross-test state bleed in the batch run, not a
regression), default JIT 314/314, jit-ir 313/314 (gpu/vertices/morph
is an expected difference from the vertex decoder taking a different
mode with this core change, not a bug).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_019SKhm9wKEQzRUsx9mTrrtQ
2026-08-12 14:02:19 +02:00
Henrik Rydgård ba148e5ec7 JIT/IRJit: Delete an old "function preloading" experiment
This caused some confusion while trying to debug #20502
2025-06-11 15:45:18 +02:00
Henrik Rydgård 83af54950f Move more core-related stuff into Core.cpp/h 2024-12-08 11:54:58 +01:00
Henrik Rydgård d3e9398cb3 Split Core_EnableStepping into Core_Break and Core_Resume 2024-11-03 17:53:42 +01:00
Henrik Rydgård 85e7ff7ac3 Target->Native renaming. More intuitive (at least to me) 2024-07-22 01:24:34 +02:00
Henrik Rydgård 9d36a08ec4 Some renaming, remove a gross hack 2024-07-21 19:12:51 +02:00
Henrik Rydgård e01ca5b057 Logging API change (refactor) (#19324)
* Rename LogType to Log

* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.

* Mac/ARM64 buildfix

* Do the same with the hle result log macros

* Rename the log names to mixed case while at it.

* iOS buildfix

* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
Henrik Rydgård 5526ef012c Store IR instructions in a large arena vector instead of loosely in each block. 2024-06-07 09:28:27 +02:00
Henrik Rydgård e75e7a0e43 Add an optimizeForInterpreter flag 2024-05-26 13:41:31 +02:00
Henrik Rydgård 46b25d20a4 Merge pull request #18637 from unknownbrackets/riscv-more
Add some more RISC-V extensions to emitter
2023-12-29 19:03:49 +01:00
Unknown W. Brackets 15cb782f85 riscv: Implement Zfa encoding.
Not yet enabled/detected.
2023-12-29 09:42:23 -08:00
Henrik Rydgård 126d88ecfc Back out clearly inconsequential/useless .reserve() calls 2023-12-29 08:27:56 +01:00
Henrik Rydgård e5af1f8bd0 Merge pull request #18560 from unknownbrackets/replacement-slice
HLE: Slice the very slow memset/memcpy variants
2023-12-17 12:35:48 +01:00
Unknown W. Brackets 053831bf4d HLE: Add mechanics for sliced replacements. 2023-12-16 09:08:58 -08:00
Herman Semenov b871e76d05 [Core/Debugger/FileLoaders/FileSystems/MIPS] Using reserve if possible 2023-12-15 13:59:19 +03:00
Unknown W. Brackets 00c80cea6e irjit: Optimize offset logging during compile.
As I guessed, this was expensive.  using a vector and reserve isn't very.
It's nice to keep this before logBlocks_ is > 0, in case it's set mid
block.
2023-09-30 15:56:18 -07:00
Henrik Rydgård 9fffa33eee Merge pull request #18234 from unknownbrackets/x86-ir-transfer
x86jit: Perform vector transfers instead of flushing to memory
2023-09-26 09:28:05 +02:00
Unknown W. Brackets 9b2fa46861 IR: Add mini native jit MIPS block profiler. 2023-09-24 23:04:29 -07:00
Unknown W. Brackets 88b6442527 irjit: Add facility for native reg transfer. 2023-09-24 16:28:29 -07:00
Unknown W. Brackets 7d0f2e43b6 irjit: Fix safety of kernel bit memory addresses. 2023-09-24 10:18:55 -07:00
Unknown W. Brackets 14e2e1ed62 x64jit: Optimize FCmpVfpuAggregate. 2023-09-23 14:31:46 -07:00
Unknown W. Brackets 7a5cdafdf3 arm64jit: Implement convert/int conversions. 2023-09-08 00:03:12 -07:00
Henrik Rydgård 0a234df037 Merge pull request #18089 from unknownbrackets/arm64jit-float
arm64jit: Implement VFPU compare, trig, couple others
2023-09-08 08:33:22 +02:00
Nemoumbra 0faa1109d2 Included <algorithm> for std::min 2023-09-07 12:14:36 +03:00
Unknown W. Brackets a1304f6ac8 arm64jit: Implement VFPU compare in IR. 2023-09-06 19:02:24 -07:00
Unknown W. Brackets 97d9a7f07f arm64jit: Implement FCmp. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets 81aeb04788 arm64jit: Implement Vec4Blend. 2023-09-05 00:10:26 -07:00
Henrik Rydgård 9690a71a14 Merge pull request #18061 from unknownbrackets/arm64-ir-jit
arm64jit: Implement most ALU and load/store in IR jit
2023-09-04 10:02:24 +02:00
Unknown W. Brackets 85b80bc9e5 arm64jit: Implement load/store in IR. 2023-09-04 00:04:36 -07:00
Unknown W. Brackets e02426cbbf arm64jit: Implement some system ops. 2023-09-03 21:16:08 -07:00
Henrik Rydgård 2f300c2023 Merge pull request #18060 from unknownbrackets/x86-jitbase
x86jit: Bake emuhack mask into jitbase
2023-09-03 22:53:23 +02:00
Unknown W. Brackets 9439a43323 riscv: Correct an overlap case, fix assert. 2023-09-03 13:29:57 -07:00
Unknown W. Brackets 0452b8b57a riscv: Account for emuhack in JITBASEREG. 2023-09-03 13:29:05 -07:00
Unknown W. Brackets 1d152a1486 x86jit: Bake emuhack mask into jitbase. 2023-09-03 12:49:36 -07:00
Unknown W. Brackets 1b756ff8c1 arm64jit: Add initial base for IR jit.
This works, but very slowly at this point.
2023-09-03 12:14:28 -07:00
Henrik Rydgård dddf63d057 Merge pull request #17993 from unknownbrackets/x86-jit-minor
x86jit: Replacements, expose for profiling better
2023-08-28 10:23:00 +02:00
Unknown W. Brackets 61a99b4bac x86jit: Implement trig/reciprocals. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets 4b1c809886 x86jit: Implement a few more float ops, shuffle. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets 2e64abd2a0 x86jit: Improve some debug labels.
Helps when running a profiler that reads these.
2023-08-27 12:51:29 -07:00
Henrik Rydgård 951c35ba71 Merge pull request #17948 from unknownbrackets/x86-ir
x86jit: Fix some issues in 32-bit
2023-08-22 09:41:10 +02:00
Unknown W. Brackets 07fa1ed573 x86jit: Automatically flush incompatible regs. 2023-08-21 21:16:54 -07:00
Unknown W. Brackets db34b85107 irjit: Allow flag-based allocation order.
Sometimes backends have needs, like XMM0/v0-only, or similar.
2023-08-21 20:46:05 -07:00
Henrik Rydgård 1e269c1d3c Merge pull request #17943 from unknownbrackets/x86-ir
Add an x86/x64 backend for IR
2023-08-21 09:21:37 +02:00
Unknown W. Brackets 08ea31f405 x86jit: Improve debug disasm. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 4e3f3860f9 x86jit: Stub out op categories to files. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets c491f701ba x86jit: Add initial IR-based jit backend.
It works, but pretty slow in some parts with everything stubbed.
2023-08-20 22:28:54 -07:00
Unknown W. Brackets 8dfc2f04d7 riscv: Use a single reg for LO/HI.
This is the same optimization we have for arm64, basically.
2023-08-20 14:49:09 -07:00
Unknown W. Brackets 36b6aa4728 riscv: Allow GPR "SIMD" without FPR SIMD. 2023-08-20 12:42:11 -07:00