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35,196 Commits 79 Branches 131 Tags
3cd882f21bf84dfae7ea25cf625c86cf30ead36d
Commit Graph
92 Commits
Author SHA1 Message Date
Unknown W. Brackets 9cfcbc46e6 Global: Cleanup initialization/pointer checks. 
Cleaning up a lot of cases of uninitialized data, unchecked return values
for failures, and similar.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets a7b7bf7826 Global: Set many read-only params as const. 
This makes what they do and which args to use clearer, if nothing else.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets c085413326 irjit: Consistently check vec4 safety. 
Just to prevent confusion/surprises, this is clearer.
 2022-11-18 19:06:50 -08:00
Unknown W. Brackets ada0674415 irjit: Allow VV2Op SIMD with exact overlap. 
None of these look at other lanes.
 2022-11-18 17:54:58 -08:00
Unknown W. Brackets 2419e5680a irjit: Correct VV2Op SIMD check. 
It's unlikely, but possible, uninitialized data could cause
IsConsecutive4() to return true when n < 4.
 2022-11-18 17:53:53 -08:00
Henrik RydgårdandGitHub e97d5498c6 Merge pull request #16306 from unknownbrackets/ir-prefixes 
irjit: Correct prefix validation
 2022-10-31 09:11:52 +01:00
Unknown W. Brackets eef29d5e95 irjit: Correct prefix validation. 
Some vcmps, etc. were perfectly valid but were forcing to interp.
This also catches more cases that should go to interp correctly.
 2022-10-30 23:15:54 -07:00
Unknown W. Brackets 56ff555309 irjit: Fix unordered float compares. 2022-10-30 21:12:59 -07:00
Unknown W. Brackets bbdc8a8f98 interp: Correct vscl/vmscl t prefix handling. 
This makes more sense.  Fixes Dissidia 012 issues.
 2022-10-29 22:43:30 -07:00
Unknown W. Brackets 3f997518f3 irjit: Handle vrot overlap more correctly. 
Sine ignores overlap, cosine does not.
 2022-10-29 22:25:25 -07:00
Unknown W. Brackets 90517ace59 irjit: Validate alignment in slow memory mode. 2022-08-21 13:24:10 -07:00
Unknown W. Brackets f32f89dd90 Global: Remove some unused variables. 2021-02-15 11:59:45 -08:00
Unknown W. Brackets 5d60fa0d0d Common: Maintain C++11 support in sign extend. 2021-01-31 08:44:02 -08:00
Unknown W. Brackets 1b00da2f3a Common: Sign extend w/func not chained casts. 
Should be clearer to read and easier to get right.
 2021-01-31 01:25:52 -08:00
Unknown W. Brackets 021f4adfad irjit: Fix mtv for INF4. 2021-01-09 12:43:50 -08:00
Unknown W. Brackets d3c06266c5 jit: Fix conditional disable flags. 2021-01-09 11:50:32 -08:00
Henrik Rydgård 9e41fafd0d Move math and some file and data conversion files out from native to Common. 
Buildfixing

Move some file util files

Buildfix

Move KeyMap.cpp/h to Core where they belong better.

libretro buildfix attempt

Move ini_file

More buildfixes
 2020-10-04 09:12:46 +02:00
Henrik RydgårdandUnknown W. Brackets f65a71d6d8 Compat: Option to use accurate dotprod for VMMUL. 
Eliminates Tekken 6 leg shaking.
 2019-08-05 11:44:52 -07:00
Henrik Rydgård 7853c90abb JIT: Split VFPU_MTX disable options. To help with #9843 2019-06-03 23:28:15 +02:00
Unknown W. Brackets c773359095 arm64jit: Tweak matrix vfpu overlap detect, etc. 
Tried making changes to them to guess at issues for #9843, but didn't find
any.  Still, I think these changes are worthwhile, if small.
 2019-06-02 22:10:20 -07:00
Unknown W. Brackets ec7cffa847 interp: Handle vtfm/vhtfm prefixes properly. 2019-04-02 18:46:39 -07:00
Unknown W. Brackets 5414c12a15 interp: Cleanup prefix/size in vcrsp/vqmul. 2019-04-02 07:12:34 -07:00
Henrik RydgårdandGitHub b346142df8 Merge pull request #11954 from unknownbrackets/vfpu-chunk5 
Fix prefix and size handling for vsbx, vsocp, and integer conv ops
 2019-04-01 17:12:03 +02:00
Unknown W. Brackets b24f84d1a2 interp: Handle prefixes on matrix init ops. 2019-03-31 17:11:24 -07:00
Unknown W. Brackets 59905de719 interp: Correct vsgn out of swizzle bounds. 2019-03-31 17:10:51 -07:00
Unknown W. Brackets b881a689c4 interp: Ignore high bit in vmfvc/vmtvc. 
Both 0 and 128 read/write the S prefix, for example.
 2019-03-31 17:09:55 -07:00
Unknown W. Brackets 175ceef583 interp: Cleanup vsocp size handling. 2019-03-31 13:52:07 -07:00
Unknown W. Brackets 4a2f8a74dc interp: Correct size handling for vi2x ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets b75690787e interp: Correct swizzle on vx2i ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets 68cdcba6c5 interp: Don't write lane 2 on single colorconv. 
Not that it's valid to use the op with that size anyway.
 2019-03-31 13:51:12 -07:00
Unknown W. Brackets 5749ae09d0 interp: Correct vmfvc register behavior. 
The target and source registers were completely wrong.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets b2e024025f interp: Handle wrong sizes of vf2h/vh2f. 
Probably not ever used, but they have consistent behavior.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets af3ed69144 interp: Mask moves to vfpu ctrl. 
These bits of the registers can't be written.
 2019-03-31 10:37:07 -07:00
Unknown W. Brackets d40ac043d4 interp: Handle prefixes for Vmmov/Vmmul/Vmscl. 
I doubt any actual code uses this, but we have some tricky VFPU bugs left,
so just trying for maximum accuracy in the interpreter.
 2019-03-31 10:37:07 -07:00
Unknown W. Brackets ec1dae57eb interp: Fix vbfy prefix handling. 2019-03-31 10:09:18 -07:00
Unknown W. Brackets d5273f589a interp: Mask value in vpfxd. 
The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
 2019-03-31 08:23:36 -07:00
Unknown W. Brackets 7dc775e54f IR: Use interp for unhandled prefix cases. 
The interpreter is not changed yet, so in theory this shouldn't change
behavior.
 2019-03-31 08:17:11 -07:00
Unknown W. Brackets 4c3aa841d3 IR: Correct vmmul optimizations. 
It's a bit confusing since it's not D = S*T, but rather D = S'*T.
 2019-03-23 15:31:10 -07:00
Unknown W. Brackets 6178a1fb33 Jit: Correct vocp prefix handling. 
See #5549.  Matches tests for various prefix settings.
 2019-02-23 09:15:26 -08:00
Unknown W. Brackets d7f40afd9d interp: Correct vocp prefix handling. 
Also, guess that vsocp also applies prefixes.  See #5549.
 2019-02-21 19:02:16 -08:00
Unknown W. Brackets 419c1fbd73 Jit: Respect flags for jit types and features. 
Left some free space for more.
 2019-02-03 14:57:08 -08:00
Henrik Rydgård 34f79904fd IR: This optimization is safe when all three regs are consecutive, so avoid disabling it unnecessarily. 2018-01-10 09:19:27 +01:00
Henrik Rydgård 18be23eccc IR: More fixes. Still something wrong with VFPU compares (not caused by this PR). 2018-01-04 19:38:36 +01:00
Henrik Rydgård 1a97f62dc9 Fix running the CPU test from the UI. 2018-01-04 18:10:41 +01:00
Unknown W. Brackets 905d2c2da6 irjit: Cleanup some invalid op handling. 
And log blocks the same way as other backends.
 2018-01-01 08:38:11 -08:00
Henrik Rydgård 22e65ba80d Get rid of ugly alignment macros and some other cruft, we now have alignas(16) from C++11 2017-08-31 01:14:51 +02:00
Unknown W. Brackets b483444fab IR: Cleanup some invalid ops. 2017-04-20 21:11:40 -07:00
Henrik RydgårdandGitHub 1091fd2dc0 Merge pull request #8840 from unknownbrackets/ir-vfpu 
Minor IR cleanup in the VFPU
 2016-07-04 10:02:52 +02:00
Unknown W. Brackets 4578c3cb54 jit-ir: Implement memory breakpoints. 
These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
 2016-07-02 16:38:30 -07:00
Unknown W. Brackets 8fab3dc91b jit-ir: Allow 3x3 and 2x2 vmmov in IR. 
While this will generate a lot of FMovs, it should still be better than
bailing to interp.
 2016-07-01 14:08:32 -07:00