Commit Graph
31 Commits
Author SHA1 Message Date
Henrik RydgårdandClaude Opus 5.5 6207ef9ec7 x86-64 IR JIT: Call the dot routine with the operands in registers
The operands go in xmm0 and xmm1 and the result comes back in edi. The routine
saves nothing: the call site flushes whatever guest state is in the registers it
clobbers, the xmms allocated last and rax, rcx, rdx, rsi and rdi, the last two
never allocated outside Windows. 32-bit x86 keeps going through the IR
interpreter.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-14 22:30:37 +02:00
Henrik RydgårdandClaude Opus 5.5 8568ae45f0 x86-64 IR JIT: Flush RCX and RDX before calls outside Windows
The System V ABI doesn't preserve them either, and the allocator hands
them out, so a helper call (vsin, vrsq and the like) could clobber a
mapped register. CPUEquivalence found it once it ran the IR JIT on
macOS: a k0 pointer in RDX came back as the helper's 1.0f.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-14 00:10:00 +02:00
Henrik RydgårdandClaude Opus 5.5 00f5e12b47 IR JIT: Don't store dead temps at exits
The IR temps don't live past the block, but FlushAll stored them anyway at
every exit (the branch operands, lwl/lwr temps, VFPU temp lanes). At an exit,
discard the ones nothing later in the block reads.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
2026-09-24 16:38:39 -06:00
Henrik Rydgård 1a89c26dc0 Warning fixes 2024-10-03 18:19:11 +02:00
Henrik Rydgård e01ca5b057 Logging API change (refactor) (#19324)
* Rename LogType to Log

* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.

* Mac/ARM64 buildfix

* Do the same with the hle result log macros

* Rename the log names to mixed case while at it.

* iOS buildfix

* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
Unknown W. Brackets 38e5b33a53 x86jit: Prefer BLENDPS to INSERTPS.
It's faster, this performs better.
2023-09-25 22:12:48 -07:00
Unknown W. Brackets 685d2acffe x86jit: Retain old lanes when there's space. 2023-09-24 17:31:25 -07:00
Unknown W. Brackets 46e704f879 x86jit: Cleanup and refactor transfer. 2023-09-24 16:58:41 -07:00
Unknown W. Brackets d9f6bae1ff x64jit: Initial reg transfer. 2023-09-24 16:28:29 -07:00
Unknown W. Brackets decccf199a x86jit: Flush floats together if possible. 2023-09-24 08:01:05 -07:00
Unknown W. Brackets 9742aaaffe x86jit: Use MOVAPS directly when we can.
May help older processors or reduce total bytes.
2023-09-24 08:01:02 -07:00
Unknown W. Brackets 07150b566a x86jit: Fix flush for special-purpose reg. 2023-09-17 09:37:57 -07:00
Unknown W. Brackets 1b756ff8c1 arm64jit: Add initial base for IR jit.
This works, but very slowly at this point.
2023-09-03 12:14:28 -07:00
Henrik Rydgård 0ecfb6b112 Merge pull request #17992 from unknownbrackets/x86-jit-float
x86jit: Implement trig instructions, couple other FPU
2023-08-28 10:20:38 +02:00
Unknown W. Brackets 61a99b4bac x86jit: Implement trig/reciprocals. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets 4b1c809886 x86jit: Implement a few more float ops, shuffle. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets 497fc09c29 x86jit: Implement divides. 2023-08-27 12:34:58 -07:00
Unknown W. Brackets d1a30334bf x86jit: Implement multiplies. 2023-08-25 00:01:03 -07:00
Unknown W. Brackets 363f2b68e1 x86jit: Implement shifts. 2023-08-25 00:01:03 -07:00
Unknown W. Brackets 00155790d6 x86jit: Add some notes for vector calls.
Let's avoid the thunks to be more similar to other backends.
2023-08-23 22:17:55 -07:00
Unknown W. Brackets 5473a5c698 x86jit: Add low MapWithFlags for Ext8to32. 2023-08-23 22:17:55 -07:00
Henrik Rydgård 7384d3d49f Debug mode buildfix 2023-08-22 16:15:07 +02:00
Unknown W. Brackets edcb156897 x86jit: Add Vec4 and Float load/store. 2023-08-22 10:39:46 +02:00
Unknown W. Brackets 07fa1ed573 x86jit: Automatically flush incompatible regs. 2023-08-21 21:16:54 -07:00
Unknown W. Brackets 55654f52b2 x86jit: Fix Store8 on i386.
Require an 8-bit capable register in mapping.
2023-08-21 21:05:51 -07:00
Unknown W. Brackets db34b85107 irjit: Allow flag-based allocation order.
Sometimes backends have needs, like XMM0/v0-only, or similar.
2023-08-21 20:46:05 -07:00
Unknown W. Brackets 40b3ff9573 x86jit: Fix spill issue. 2023-08-21 08:23:58 -07:00
Unknown W. Brackets 104b6d8c15 x86jit: Implement some basic arithmetic. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 4e7f8cf213 x86jit: Implement load/store. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets a47b4424e5 x86jit: Fix some silly mistakes. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets c491f701ba x86jit: Add initial IR-based jit backend.
It works, but pretty slow in some parts with everything stubbed.
2023-08-20 22:28:54 -07:00