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https://github.com/hrydgard/ppsspp.git
synced 2026-10-14 15:00:30 +02:00
x86jit: Cleanup and refactor transfer.
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@@ -470,172 +470,175 @@ bool X64IRRegCache::TransferNativeReg(IRNativeReg nreg, IRNativeReg dest, MIPSLo
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_assert_msg_(oldlanes != 0, "TransferNativeReg encountered nreg mismatch");
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_assert_msg_(oldlanes != lanes, "TransferNativeReg transfer to same lanecount, misaligned?");
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if (lanes == 1) {
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// Okay, start by storing if dirty.
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if (nr[nreg].isDirty) {
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StoreNativeReg(nreg, oldfirst, oldlanes);
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nr[nreg].isDirty = false;
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}
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// Next, shuffle the desired element into first place.
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u8 shuf = VFPU_SWIZZLE(mr[first].lane, mr[first].lane, mr[first].lane, mr[first].lane);
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if (mr[first].lane > 0 && cpu_info.bAVX && dest != nreg) {
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emit_->VSHUFPS(128, FromNativeReg(dest), FromNativeReg(nreg), ::R(FromNativeReg(nreg)), shuf);
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} else if (mr[first].lane <= 0 && dest != nreg) {
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emit_->MOVAPS(FromNativeReg(dest), ::R(FromNativeReg(nreg)));
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} else if (mr[first].lane > 0) {
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if (dest != nreg)
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emit_->MOVAPS(FromNativeReg(dest), ::R(FromNativeReg(nreg)));
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emit_->SHUFPS(FromNativeReg(dest), ::R(FromNativeReg(dest)), shuf);
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}
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// TODO: Consider moving the others to free regs if available? Likely will be wanted later.
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// Now update accounting.
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for (int i = 0; i < oldlanes; ++i) {
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auto &mreg = mr[oldfirst + i];
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if (oldfirst + i == first) {
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mreg.lane = 0;
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mreg.nReg = dest;
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} else {
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// No longer in a register.
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mreg.nReg = -1;
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mreg.lane = -1;
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mreg.loc = MIPSLoc::MEM;
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}
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}
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if (dest != nreg) {
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nr[dest].isDirty = nr[nreg].isDirty;
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nr[nreg].mipsReg = -1;
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nr[nreg].isDirty = false;
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}
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nr[dest].mipsReg = first;
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if (lanes == 1 && TransferVecTo1(nreg, dest, first, oldlanes))
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return true;
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if (oldlanes == 1 && Transfer1ToVec(nreg, dest, first, lanes))
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return true;
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}
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if ((lanes == 4 || lanes == 2) && oldlanes == 1) {
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X64Reg cur[4]{};
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int numInRegs = 0;
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int numDirty = 0;
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bool unavail = false;
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for (int i = 0; i < lanes; ++i) {
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if (mr[first + i].lane != -1 || (i != 0 && mr[first + i].spillLockIRIndex >= irIndex_)) {
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unavail = true;
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break;
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}
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if (mr[first + i].nReg == -1) {
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cur[i] = INVALID_REG;
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} else {
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cur[i] = FromNativeReg(mr[first + i].nReg);
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numInRegs++;
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if (nr[cur[i]].isDirty)
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numDirty++;
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}
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}
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if (numInRegs == 0)
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unavail = true;
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bool handled = false;
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if (!unavail) {
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// If everything's currently in a reg, move it into this reg.
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if (lanes == 4) {
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if (cur[0] == INVALID_REG) {
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cur[0] = FromNativeReg(dest);
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emit_->MOVSS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 0)));
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numInRegs++;
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}
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// A lot of other methods are possible, but seem to make things slower in practice.
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if (numInRegs == 4) {
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// y = yw##, x = xz##, x = xyzw.
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emit_->UNPCKLPS(cur[1], ::R(cur[3]));
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emit_->UNPCKLPS(cur[0], ::R(cur[2]));
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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handled = true;
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} else if (numInRegs == 2 && cur[1] != INVALID_REG) {
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// x = xy##, then load zw.
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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emit_->MOVHPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 2)));
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handled = true;
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} else if (cpu_info.bSSE4_1 && cur[1] != INVALID_REG && cur[2] != INVALID_REG) {
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// x = xz##, z=w###, y=yw##, x=xyzw.
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emit_->UNPCKLPS(cur[0], ::R(cur[2]));
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emit_->MOVSS(cur[2], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 3)));
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emit_->UNPCKLPS(cur[1], ::R(cur[2]));
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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handled = true;
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} else if (cpu_info.bSSE4_1 && numDirty != 0 && cur[1] != INVALID_REG && cur[3] != INVALID_REG) {
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// y = yw##, load z into x[1], x = xyzw.
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emit_->UNPCKLPS(cur[1], ::R(cur[3]));
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emit_->INSERTPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 2)), 1);
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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handled = true;
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} else if (cpu_info.bSSE4_1 && numDirty != 0 && cur[2] != INVALID_REG && cur[3] != INVALID_REG) {
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// load y to x[1], z = zw##, x = xyzw.
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emit_->INSERTPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 1)), 1);
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emit_->UNPCKLPS(cur[2], ::R(cur[3]));
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emit_->MOVLHPS(cur[0], cur[2]);
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handled = true;
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} else if (cpu_info.bSSE4_1) {
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// TODO: This might be worse than flushing depending?
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for (int i = 1; i < 4; ++i) {
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if (cur[i] == INVALID_REG)
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emit_->INSERTPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + i)), i);
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else
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emit_->INSERTPS(cur[0], ::R(cur[i]), i, 0);
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}
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handled = true;
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}
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} else if (lanes == 2) {
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if (cur[0] != INVALID_REG && cur[1] != INVALID_REG) {
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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handled = true;
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} else if (cur[0] != INVALID_REG && cpu_info.bSSE4_1) {
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emit_->INSERTPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 1)), 1);
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handled = true;
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}
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}
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}
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if (handled) {
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mr[first].lane = 0;
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for (int i = 0; i < lanes; ++i) {
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if (mr[first + i].nReg != -1) {
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// If this was dirty, the combined reg is now dirty.
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if (nr[mr[first + i].nReg].isDirty)
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nr[dest].isDirty = true;
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// Throw away the other register we're no longer using.
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if (i != 0)
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DiscardNativeReg(mr[first + i].nReg);
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}
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// And set it as using the new one.
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mr[first + i].lane = i;
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mr[first + i].loc = type;
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mr[first + i].nReg = dest;
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}
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if (cur[0] != FromNativeReg(dest))
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emit_->MOVAPS(FromNativeReg(dest), ::R(cur[0]));
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if (dest != nreg) {
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nr[dest].mipsReg = first;
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nr[nreg].mipsReg = -1;
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nr[nreg].isDirty = false;
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}
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return true;
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}
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}
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}
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return IRNativeRegCacheBase::TransferNativeReg(nreg, dest, type, first, lanes, flags);
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}
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bool X64IRRegCache::TransferVecTo1(IRNativeReg nreg, IRNativeReg dest, IRReg first, int oldlanes) {
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// Okay, start by storing if dirty.
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// TODO: Consider moving the others to free regs if available? Likely will be wanted later.
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IRReg oldfirst = nr[nreg].mipsReg;
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if (nr[nreg].isDirty) {
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StoreNativeReg(nreg, oldfirst, oldlanes);
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nr[nreg].isDirty = false;
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}
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// Next, shuffle the desired element into first place.
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u8 shuf = VFPU_SWIZZLE(mr[first].lane, mr[first].lane, mr[first].lane, mr[first].lane);
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if (mr[first].lane > 0 && cpu_info.bAVX && dest != nreg) {
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emit_->VPERMILPS(128, FromNativeReg(dest), ::R(FromNativeReg(nreg)), shuf);
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} else if (mr[first].lane <= 0 && dest != nreg) {
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emit_->MOVAPS(FromNativeReg(dest), ::R(FromNativeReg(nreg)));
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} else if (mr[first].lane > 0) {
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if (mr[first].lane == 2) {
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emit_->MOVHLPS(FromNativeReg(dest), FromNativeReg(nreg));
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} else {
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if (dest != nreg)
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emit_->MOVAPS(FromNativeReg(dest), ::R(FromNativeReg(nreg)));
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emit_->SHUFPS(FromNativeReg(dest), ::R(FromNativeReg(dest)), shuf);
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}
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}
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// Now update accounting.
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for (int i = 0; i < oldlanes; ++i) {
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auto &mreg = mr[oldfirst + i];
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if (oldfirst + i == first) {
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mreg.lane = 0;
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mreg.nReg = dest;
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} else {
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// No longer in a register.
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mreg.nReg = -1;
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mreg.lane = -1;
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mreg.loc = MIPSLoc::MEM;
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}
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}
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if (dest != nreg) {
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nr[dest].isDirty = nr[nreg].isDirty;
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nr[nreg].mipsReg = -1;
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nr[nreg].isDirty = false;
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}
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nr[dest].mipsReg = first;
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return true;
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}
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bool X64IRRegCache::Transfer1ToVec(IRNativeReg nreg, IRNativeReg dest, IRReg first, int lanes) {
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X64Reg cur[4]{};
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int numInRegs = 0;
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int numDirty = 0;
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for (int i = 0; i < lanes; ++i) {
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if (mr[first + i].lane != -1 || (i != 0 && mr[first + i].spillLockIRIndex >= irIndex_)) {
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// Can't do it, either double mapped or overlapping vec.
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return false;
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}
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if (mr[first + i].nReg == -1) {
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cur[i] = INVALID_REG;
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} else {
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cur[i] = FromNativeReg(mr[first + i].nReg);
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numInRegs++;
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if (nr[cur[i]].isDirty)
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numDirty++;
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}
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}
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// Shouldn't happen, this should only get called to transfer one in a reg.
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if (numInRegs == 0)
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return false;
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// If everything's currently in a reg, move it into this reg.
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if (lanes == 4) {
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if (cur[0] == INVALID_REG) {
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cur[0] = FromNativeReg(dest);
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emit_->MOVSS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 0)));
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numInRegs++;
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}
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// A lot of other methods are possible, but seem to make things slower in practice.
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if (numInRegs == 4) {
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// y = yw##, x = xz##, x = xyzw.
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emit_->UNPCKLPS(cur[1], ::R(cur[3]));
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emit_->UNPCKLPS(cur[0], ::R(cur[2]));
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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} else if (numInRegs == 2 && cur[1] != INVALID_REG) {
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// x = xy##, then load zw.
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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emit_->MOVHPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 2)));
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} else if (cur[1] != INVALID_REG && cur[2] != INVALID_REG) {
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// x = xz##, z=w###, y=yw##, x=xyzw.
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emit_->UNPCKLPS(cur[0], ::R(cur[2]));
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emit_->MOVSS(cur[2], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 3)));
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emit_->UNPCKLPS(cur[1], ::R(cur[2]));
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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} else if (cpu_info.bSSE4_1 && numDirty != 0 && cur[1] != INVALID_REG && cur[3] != INVALID_REG) {
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// y = yw##, load z into x[1], x = xyzw.
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emit_->UNPCKLPS(cur[1], ::R(cur[3]));
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emit_->INSERTPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 2)), 1);
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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} else if (cpu_info.bSSE4_1 && numDirty != 0 && cur[2] != INVALID_REG && cur[3] != INVALID_REG) {
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// load y to x[1], z = zw##, x = xyzw.
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emit_->INSERTPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 1)), 1);
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emit_->UNPCKLPS(cur[2], ::R(cur[3]));
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emit_->MOVLHPS(cur[0], cur[2]);
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} else if (cpu_info.bSSE4_1) {
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// TODO: This might be worse than flushing depending?
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for (int i = 1; i < 4; ++i) {
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if (cur[i] == INVALID_REG)
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emit_->INSERTPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + i)), i);
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else
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emit_->INSERTPS(cur[0], ::R(cur[i]), i, 0);
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}
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} else {
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return false;
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}
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} else if (lanes == 2) {
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if (cur[0] != INVALID_REG && cur[1] != INVALID_REG) {
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emit_->UNPCKLPS(cur[0], ::R(cur[1]));
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} else if (cur[0] != INVALID_REG && cpu_info.bSSE4_1) {
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emit_->INSERTPS(cur[0], MDisp(CTXREG, -128 + GetMipsRegOffset(first + 1)), 1);
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} else {
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return false;
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}
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} else {
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return false;
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}
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mr[first].lane = 0;
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for (int i = 0; i < lanes; ++i) {
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if (mr[first + i].nReg != -1) {
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// If this was dirty, the combined reg is now dirty.
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if (nr[mr[first + i].nReg].isDirty)
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nr[dest].isDirty = true;
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// Throw away the other register we're no longer using.
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if (i != 0)
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DiscardNativeReg(mr[first + i].nReg);
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}
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// And set it as using the new one.
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mr[first + i].lane = i;
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mr[first + i].loc = MIPSLoc::FREG;
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mr[first + i].nReg = dest;
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}
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if (cur[0] != FromNativeReg(dest))
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emit_->MOVAPS(FromNativeReg(dest), ::R(cur[0]));
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if (dest != nreg) {
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nr[dest].mipsReg = first;
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nr[nreg].mipsReg = -1;
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nr[nreg].isDirty = false;
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}
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return true;
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}
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void X64IRRegCache::SetNativeRegValue(IRNativeReg nreg, uint32_t imm) {
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X64Reg r = FromNativeReg(nreg);
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_dbg_assert_(nreg >= 0 && nreg < NUM_X_REGS);
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@@ -120,6 +120,9 @@ protected:
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bool TransferNativeReg(IRNativeReg nreg, IRNativeReg dest, MIPSLoc type, IRReg first, int lanes, MIPSMap flags) override;
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private:
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bool TransferVecTo1(IRNativeReg nreg, IRNativeReg dest, IRReg first, int oldlanes);
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bool Transfer1ToVec(IRNativeReg nreg, IRNativeReg dest, IRReg first, int lanes);
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IRNativeReg GPRToNativeReg(Gen::X64Reg r) {
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return (IRNativeReg)r;
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}
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