Henrik Rydgård and Claude Opus 5.5
961726dc88
VFPU: vrnds takes its seed from the vs field
...
The toolchain encodes vrnds's operand in vs and leaves vd zero, so we
always seeded from S000. Resistance: Retribution reseeds per particle
from S620, which made every particle in its smoke and explosions take
new random values each frame. They flickered, and some never drew.
Hardware test: cpu/vfpu/vrnd (vs and vd fields).
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-15 00:09:25 +02:00
Henrik Rydgård and Claude Opus 5.5
124f86d7d0
VFPU: Decode prefixes with shared helpers
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The prefix fields were decoded by hand in the interpreter, the IR frontend,
JitState, MIPSState and the disassembler, with three copies of the constant
table. They now share small decoders and one table, in MIPS.h. The backends'
Vec4Shuffle lane decoding gets a helper of its own in IRInst.h.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
2026-10-14 21:34:05 +02:00
Thomas Lamb
bf67ed300d
Fix assembly/disassembly for various VFPU opcodes
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Update armips for VFPU instruction parsing changes (Kingcom/armips#257 )
- fix transposed matrix register encodings (e.g. `vmidt.p E220` was assembling to `vmidt.p E202`)
- fix immediate size for `vwbn.s` (is 8 bits, was limited to 5 bits)
- fix `vd` register size for `vsocp.s/p`
- fix `vhtfm2.p` and `vhtfm3.t` encoding
- add missing instruction `vhtfm4.q`
Fix `v(h)tfmX` disassembly (handle irregular vector size encoding)
Fix `vsocp.s/p` disassembly (`vd` is double the size of `vs`)
2026-08-11 10:10:56 -04:00
Thomas Lamb
d1656d425a
Improve debugger assemble/disassemble compatiblity
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Update armips for VFPU instruction parsing changes:
- Kingcom/armips#255
- Kingcom/armips#256
Remove brackets from VFPU instruction `vpfx*` params
Rename VFPU instruction `vuc2i.s` to `vuc2ifs.s`
Add brackets to VFPU instruction `vpfxd` saturation operations (i.e. [0:1] & [-1:1])
Rename FPU instructions `c.$OP` to `c.$OP.s`
Fix VFPU instruction `vuc2ifs.s` `vd` size in disassembly
Replace `CC[imm3]` with `imm3` in VFPU instructions `vcmov*` & `bv*` disassembly
2026-07-07 20:30:51 -04:00
Henrik Rydgård
3e198c53b2
More include cleanup
2024-12-18 13:57:26 +01:00
Henrik Rydgård
e3177ac870
Make some global string pointers const, not just the strings.
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Minor cleanup.
2023-12-29 14:09:45 +01:00
Henrik Rydgård
1ef1478cc8
Remove more impossibilities (GetMtxSize)
2023-06-04 11:48:43 +02:00
Henrik Rydgård
a92cca2575
Don't check for impossibilities. Minor speedup for GetVecSize.
2023-06-04 11:28:39 +02:00
Unknown W. Brackets
5b1235537f
Debugger: Make disasm more thread safe.
2023-04-29 09:56:17 -07:00
Unknown W. Brackets
6da10463f9
Debugger: Make reg names safer, stop using v000.
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Better to use S000, etc. as that's more clear throughout.
2023-04-29 09:48:33 -07:00
Unknown W. Brackets
46101581c0
Core: Cleanup disasm buffer usage.
2023-04-29 09:07:25 -07:00
Unknown W. Brackets
1fc74b1980
Debugger: Format vfpu offsets as hex.
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Let's be consistent across FP and VFPU, it's confusing otherwise.
2023-04-09 10:44:19 -07:00
Unknown W. Brackets
f6640cf5e5
Debugger: Fix viim disassembly.
2023-04-09 10:36:51 -07:00
Unknown W. Brackets
5233a3bc84
Debugger: Cleanup some sign extends in disassembly.
2023-04-09 10:36:20 -07:00
kotcrab
7a124d84ae
Fix disassembly of vcst
2021-09-25 19:34:41 +02:00
kotcrab
4bdba8ae6f
Fix disassembly of vmfvc and vmtvc
2021-09-25 16:33:07 +02:00
kotcrab
b7a64750ed
Fix vcrs disassembly
2019-10-30 22:35:13 +01:00
Unknown W. Brackets
22940f0393
Debugger: Avoid asserts in disassembly.
2018-06-08 06:59:18 -07:00
Kingcom
6b29fe9d60
Change VROT disassembly
2014-11-29 18:33:33 +01:00
Kingcom
479c8646a2
Change vpfxs/r/t disassembly syntax
2014-11-12 00:09:57 +01:00
Unknown W. Brackets
737c96eced
More cstring includes, grr.
2014-03-15 12:03:33 -07:00
lioncash
b9886942a7
Fix some vertical alignments in misc Core source files.
2014-03-03 11:16:53 -05:00
Unknown W. Brackets
a69ddf840c
Fix some formatting warnings.
2013-12-01 11:21:15 -08:00
Unknown W. Brackets
ec05146ffd
Improve vfpu disasm for a few instructions.
2013-11-29 10:07:15 -08:00
Unknown W. Brackets
109ad17ac6
Use a typesafe struct for opcodes.
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Also, correctly read delayslots using Read_Instruction on ARM.
2013-08-24 15:36:24 -07:00
Henrik Rydgard
a385ec6056
MIPSDis cleanup, allow mfv zero, 255 (appears to be used to flush VFPU state or something)
2012-11-23 10:35:28 +01:00
Henrik Rydgard
772b599041
Resurrect vmfvc/vmtvc, they are different from mfvc/mtvc
2012-11-22 22:30:44 +01:00
Henrik Rydgard
232b84cd10
Assorted FPU/VFPU fixes, after adding more tests.
2012-11-22 18:13:48 +01:00
Henrik Rydgard
d572d40c36
More warning fixing
2012-11-18 23:35:02 +01:00
Henrik Rydgard
64cc573703
Switch to "GPL 2.0 or later" for various reasons. I wrote most of the code I imported from Dolphin (which is GPL2-but-not-later), so it should be OK.
2012-11-04 23:24:00 +01:00
Henrik Rydgard
4f7ad15758
Add snapshot of the whole source code.
2012-11-01 16:19:01 +01:00
