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15,011 Commits 79 Branches 131 Tags
1c78e29c7944e41093bb35ee252e2102900be52b
Commit Graph
6678 Commits
Author SHA1 Message Date
Henrik Rydgard 1c78e29c79 x86 jit: For clarity, use TEMPREG where it doesn't matter that it's EAX. 
Might have missed a few places.
 2014-11-16 17:38:26 +01:00
Henrik Rydgard 8b90f881b8 x86 jit: A tiny optimization and a tiny bugfix 2014-11-16 16:46:35 +01:00
sum2012 395ff97ecf Fix min mac problem 2014-11-13 23:57:16 +08:00
sum2012 feb23d717d Fix Wrong MAC address by old version by "Change MAC address" 2014-11-13 23:56:08 +08:00
Sacha a95500c930 Successful build on GCW-Zero. 2014-11-14 01:41:43 +10:00
Henrik Rydgård 653ac91d6a Merge pull request #7089 from sum2012/MAC 
Fix Wrong MAC address by "Change MAC address"
 2014-11-13 16:05:55 +01:00
sum2012 486c32b91b Fix 0A to 0F 2014-11-13 22:57:57 +08:00
sum2012 05b293c632 No need bracket 2014-11-13 22:20:29 +08:00
sum2012 122c3b866e Fix Wrong MAC address by "Change MAC address" 
Part 1 of 7088
 2014-11-13 22:13:57 +08:00
xSacha 57e4088216 Introduce fake vertex decoder JIT as well. 
Compiles and links on CI20 but gets unknown crash in GL driver.
 2014-11-13 17:10:29 +10:00
Sacha c421617c84 Fix Qt build by building Arm disassembler for all platforms. 2014-11-13 00:55:00 +10:00
Sacha a0086f6412 Introduce a Fake JIT for generic builds. 2014-11-13 00:09:51 +10:00
Kingcom 479c8646a2 Change vpfxs/r/t disassembly syntax 2014-11-12 00:09:57 +01:00
Henrik Rydgård a8b310ed34 Merge pull request #7078 from unknownbrackets/jit-minor 
x86jit: Use simd for vcmp comparisons where possible
 2014-11-11 14:58:21 +01:00
Sacha 1ba9103cef Better support for new archs. 2014-11-11 22:55:49 +10:00
Unknown W. Brackets 096b41cceb x86jit: Interleave reg usage in vcmp. 2014-11-10 23:22:04 -08:00
Unknown W. Brackets 0e1aa35e84 x86jit: Just do the ES/NS compare once. 2014-11-10 23:04:38 -08:00
Unknown W. Brackets 2758e8fa3c x86jit: Optimize vcmp for single and simd. 2014-11-10 23:04:37 -08:00
Unknown W. Brackets 94e29da6c4 Fix a typo in the mips assembler. 
Oops, this should be a unique value of course.
 2014-11-10 09:13:11 -08:00
Unknown W. Brackets 01c2b88911 Avoid signed ints, seems to cause clang errors. 2014-11-09 16:49:24 -08:00
Henrik Rydgård 7fbe8ba898 Merge pull request #7076 from unknownbrackets/debugger 
Add VFPU instructions to the mips asm tables
 2014-11-10 00:57:08 +01:00
Unknown W. Brackets 370fb86379 Add VFPU instructions to the mips asm tables. 2014-11-09 15:14:07 -08:00
Unknown W. Brackets 86e3739a3e x86jit: Optimize some cases of ins/ext. 
They happen but are minor.
 2014-11-09 09:22:29 -08:00
Unknown W. Brackets e05263af32 x86jit: Allow EBX sign extension for 32-bit. 2014-11-09 09:07:52 -08:00
Unknown W. Brackets 8dbd3c3b9c x86jit: Don't lie about ZERO when it's not an imm. 2014-11-09 08:27:02 -08:00
Unknown W. Brackets d0a2ced2f9 x86jit: Flip cc in stl* to avoid reg loads. 
Unfortunately, this zero thing is now concerning me...
 2014-11-09 08:15:39 -08:00
Unknown W. Brackets 59f491eddb x86jit: Micro optimize slt* a bit. 
This improves their performance and hopefully latency.  It also avoids
filling registers that are not likely to be used again.

Fixed a small mistake.
 2014-11-09 07:23:44 -08:00
Henrik Rydgard 18495a452d Rename an enum 2014-11-09 14:55:23 +01:00
Henrik Rydgard a19d0b648a x86 jit: Add a simple speedhack (ignore masking stack pointers) but disable due to low impact. 2014-11-09 14:54:39 +01:00
Henrik Rydgard a528921f3c x86 JIT: EBX was free in 32-bit mode, let's use it in the regcache. 2014-11-09 12:55:17 +01:00
Henrik Rydgard 1eec10b614 Properly prevent loading ISO to RAM in 32-bit mode (could have been enabled in 64-bit mode where the UI exists) 2014-11-09 12:53:31 +01:00
Henrik Rydgard db853d8513 Collapse sequences of "int3" (padding after block linking) in x86 disassembly. 2014-11-09 12:10:37 +01:00
Henrik Rydgard 5888b3bdc4 Revert "x86jit: Micro optimize slt* a bit." 
This reverts commit ee66596b8d.

Broke a lot of games, probably some small bug.

Conflicts:
	Core/MIPS/x86/CompALU.cpp
 2014-11-09 12:07:21 +01:00
Henrik Rydgard 5bcdecc26b unittest: Have the JIT harness print disassembly, to make it easy to inspect results. 2014-11-09 12:03:04 +01:00
Unknown W. Brackets 313d9e95c7 Clarify a comment. 2014-11-09 01:05:03 -08:00
Unknown W. Brackets ee66596b8d x86jit: Micro optimize slt* a bit. 
This improves their performance and hopefully latency.  It also avoids
filling registers that are not likely to be used again.
 2014-11-08 22:54:03 -08:00
Unknown W. Brackets 27d8108bb2 x86jit: Optimize loads of 0 into fp regs. 2014-11-08 18:41:16 -08:00
Unknown W. Brackets 7d8858687e x86jit: Avoid speculative loads in mtc1/mfc1. 2014-11-08 18:35:15 -08:00
Unknown W. Brackets 57caa95273 x86jit: Implement round.w.s and friends. 
They are not terribly fast, though, updating MXCSR.
 2014-11-08 17:59:38 -08:00
Unknown W. Brackets 3908e0f445 x86jit: Small optimization for add.s f1, f2, f2. 
Doubles the speed of that particular case.  Biggest difference is not
loading fd for no reason.
 2014-11-08 17:32:53 -08:00
Unknown W. Brackets f9893c29ce x86jit: Very small optimization to c.nge.s. 2014-11-08 17:01:02 -08:00
Unknown W. Brackets 78dfe43776 x86jit: Optimize neg.s and abs.s a tiny bit. 
Same reg is probably a common case, improves micro benchmark.
 2014-11-08 16:50:41 -08:00
Unknown W. Brackets bed0d0b059 x86jit: Improve cvt.w.s when fd is loaded or fs. 
We have no need to store it.
 2014-11-08 16:40:54 -08:00
Unknown W. Brackets 1917d946ea x86jit: Micro optimize cvt.s.w a bit. 
This implementation is about 5x faster for micro benchmarks.  Little
impact to overall perf in games I tested, though.
 2014-11-08 13:30:38 -08:00
Unknown W. Brackets 671dee85c7 x86jit: Micro optimize vi2f a little bit. 
This didn't help overall perf much but micro benchmarks are better.
 2014-11-08 13:07:01 -08:00
Unknown W. Brackets c29b126357 x86jit: Oops, can't have an imm here. 2014-11-08 12:41:48 -08:00
Unknown W. Brackets c0be19edb6 x86jit: Simplify vavg a bit. 2014-11-08 12:40:04 -08:00
Unknown W. Brackets 761e269e5f x86jit: Avoid some regcache pollution. 2014-11-08 12:38:08 -08:00
Unknown W. Brackets bc7497857a x86jit: Micro optimize vi2x a bit with ssse3/sse4. 
Both are small wins.
 2014-11-08 12:13:26 -08:00
Unknown W. Brackets 0e646f748a x86jit: Implement vi2x instructions. 
Also, my opcodes were wrong in the test (shifted the pair bit the wrong
way, oops.)

AFAICT, there's no reason PSRAD/etc. were not encoding REX...
 2014-11-08 12:13:26 -08:00