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x86 jit: For clarity, use TEMPREG where it doesn't matter that it's EAX.

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Might have missed a few places.
This commit is contained in:
Henrik Rydgard
2014-11-16 17:38:26 +01:00
parent 8b90f881b8
commit 1c78e29c79
4 changed files with 75 additions and 71 deletions
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Core/MIPS/x86/CompALU.cpp
+38 -37
View File
@@ -123,8 +123,8 @@ namespace MIPSComp
bool needsTemp = !HasLowSubregister(gpr.R(rt)) || rt == rs;
if (needsTemp) {
CMP(32, gpr.R(rs), Imm32(suimm));
SETcc(CC_L, R(EAX));
MOVZX(32, 8, gpr.RX(rt), R(EAX));
SETcc(CC_L, R(TEMPREG));
MOVZX(32, 8, gpr.RX(rt), R(TEMPREG));
} else {
XOR(32, gpr.R(rt), gpr.R(rt));
CMP(32, gpr.R(rs), Imm32(suimm));
@@ -145,8 +145,8 @@ namespace MIPSComp
bool needsTemp = !HasLowSubregister(gpr.R(rt)) || rt == rs;
if (needsTemp) {
CMP(32, gpr.R(rs), Imm32(suimm));
SETcc(CC_B, R(EAX));
MOVZX(32, 8, gpr.RX(rt), R(EAX));
SETcc(CC_B, R(TEMPREG));
MOVZX(32, 8, gpr.RX(rt), R(TEMPREG));
} else {
XOR(32, gpr.R(rt), gpr.R(rt));
CMP(32, gpr.R(rs), Imm32(suimm));
@@ -218,11 +218,11 @@ namespace MIPSComp
{
gpr.Lock(rd, rs);
gpr.MapReg(rd, rd == rs, true);
BSR(32, EAX, gpr.R(rs));
BSR(32, TEMPREG, gpr.R(rs));
FixupBranch notFound = J_CC(CC_Z);
MOV(32, gpr.R(rd), Imm32(31));
SUB(32, gpr.R(rd), R(EAX));
SUB(32, gpr.R(rd), R(TEMPREG));
FixupBranch skip = J();
SetJumpTarget(notFound);
@@ -249,13 +249,13 @@ namespace MIPSComp
{
gpr.Lock(rd, rs);
gpr.MapReg(rd, rd == rs, true);
MOV(32, R(EAX), gpr.R(rs));
NOT(32, R(EAX));
BSR(32, EAX, R(EAX));
MOV(32, R(TEMPREG), gpr.R(rs));
NOT(32, R(TEMPREG));
BSR(32, TEMPREG, R(TEMPREG));
FixupBranch notFound = J_CC(CC_Z);
MOV(32, gpr.R(rd), Imm32(31));
SUB(32, gpr.R(rd), R(EAX));
SUB(32, gpr.R(rd), R(TEMPREG));
FixupBranch skip = J();
SetJumpTarget(notFound);
@@ -356,13 +356,13 @@ namespace MIPSComp
NOT(32, gpr.R(rd));
}
} else {
// Use EAX as a temporary if we'd overwrite it.
// Use TEMPREG as a temporary if we'd overwrite it.
if (rd == rt)
MOV(32, R(EAX), gpr.R(rt));
MOV(32, R(TEMPREG), gpr.R(rt));
gpr.MapReg(rd, rs == rd, true);
if (rs != rd)
MOV(32, gpr.R(rd), gpr.R(rs));
(this->*arith)(32, gpr.R(rd), rd == rt ? R(EAX) : gpr.R(rt));
(this->*arith)(32, gpr.R(rd), rd == rt ? R(TEMPREG) : gpr.R(rt));
if (invertResult) {
NOT(32, gpr.R(rd));
}
@@ -485,8 +485,8 @@ namespace MIPSComp
bool needsTemp = !HasLowSubregister(gpr.R(rd)) || rd == rt || rd == rs;
if (needsTemp) {
CMP(32, gpr.R(lhs), gpr.R(rhs));
SETcc(cc, R(EAX));
MOVZX(32, 8, gpr.RX(rd), R(EAX));
SETcc(cc, R(TEMPREG));
MOVZX(32, 8, gpr.RX(rd), R(TEMPREG));
} else {
XOR(32, gpr.R(rd), gpr.R(rd));
CMP(32, gpr.R(lhs), gpr.R(rhs));
@@ -525,8 +525,8 @@ namespace MIPSComp
bool needsTemp = !HasLowSubregister(gpr.R(rd)) || rd == rt || rd == rs;
if (needsTemp) {
CMP(32, gpr.R(lhs), gpr.R(rhs));
SETcc(cc, R(EAX));
MOVZX(32, 8, gpr.RX(rd), R(EAX));
SETcc(cc, R(TEMPREG));
MOVZX(32, 8, gpr.RX(rd), R(TEMPREG));
} else {
XOR(32, gpr.R(rd), gpr.R(rd));
CMP(32, gpr.R(lhs), gpr.R(rhs));
@@ -756,13 +756,13 @@ namespace MIPSComp
{
gpr.Lock(rs, rt);
gpr.MapReg(rt, true, true);
MOV(32, R(EAX), gpr.R(rs));
AND(32, R(EAX), Imm32(sourcemask));
MOV(32, R(TEMPREG), gpr.R(rs));
AND(32, R(TEMPREG), Imm32(sourcemask));
if (pos != 0) {
SHL(32, R(EAX), Imm8(pos));
SHL(32, R(TEMPREG), Imm8(pos));
}
AND(32, gpr.R(rt), Imm32(destmask));
OR(32, gpr.R(rt), R(EAX));
OR(32, gpr.R(rt), R(TEMPREG));
gpr.UnlockAll();
}
}
@@ -794,8 +794,8 @@ namespace MIPSComp
// Work around the byte-register addressing problem.
if (gpr.R(rt).IsSimpleReg() && !HasLowSubregister(gpr.R(rt)))
{
MOV(32, R(EAX), gpr.R(rt));
MOVSX(32, 8, gpr.RX(rd), R(EAX));
MOV(32, R(TEMPREG), gpr.R(rt));
MOVSX(32, 8, gpr.RX(rd), R(TEMPREG));
}
else
{
@@ -829,31 +829,31 @@ namespace MIPSComp
if (rd != rt)
MOV(32, gpr.R(rd), gpr.R(rt));
LEA(32, EAX, MScaled(gpr.RX(rd), 2, 0));
LEA(32, TEMPREG, MScaled(gpr.RX(rd), 2, 0));
SHR(32, gpr.R(rd), Imm8(1));
XOR(32, gpr.R(rd), R(EAX));
XOR(32, gpr.R(rd), R(TEMPREG));
AND(32, gpr.R(rd), Imm32(0x55555555));
XOR(32, gpr.R(rd), R(EAX));
XOR(32, gpr.R(rd), R(TEMPREG));
LEA(32, EAX, MScaled(gpr.RX(rd), 4, 0));
LEA(32, TEMPREG, MScaled(gpr.RX(rd), 4, 0));
SHR(32, gpr.R(rd), Imm8(2));
XOR(32, gpr.R(rd), R(EAX));
XOR(32, gpr.R(rd), R(TEMPREG));
AND(32, gpr.R(rd), Imm32(0x33333333));
XOR(32, gpr.R(rd), R(EAX));
XOR(32, gpr.R(rd), R(TEMPREG));
MOV(32, R(EAX), gpr.R(rd));
SHL(32, R(EAX), Imm8(4));
MOV(32, R(TEMPREG), gpr.R(rd));
SHL(32, R(TEMPREG), Imm8(4));
SHR(32, gpr.R(rd), Imm8(4));
XOR(32, gpr.R(rd), R(EAX));
XOR(32, gpr.R(rd), R(TEMPREG));
AND(32, gpr.R(rd), Imm32(0x0F0F0F0F));
XOR(32, gpr.R(rd), R(EAX));
XOR(32, gpr.R(rd), R(TEMPREG));
MOV(32, R(EAX), gpr.R(rd));
SHL(32, R(EAX), Imm8(8));
MOV(32, R(TEMPREG), gpr.R(rd));
SHL(32, R(TEMPREG), Imm8(8));
SHR(32, gpr.R(rd), Imm8(8));
XOR(32, gpr.R(rd), R(EAX));
XOR(32, gpr.R(rd), R(TEMPREG));
AND(32, gpr.R(rd), Imm32(0x00FF00FF));
XOR(32, gpr.R(rd), R(EAX));
XOR(32, gpr.R(rd), R(TEMPREG));
ROL(32, gpr.R(rd), Imm8(16));
@@ -959,6 +959,7 @@ namespace MIPSComp
gpr.KillImmediate(MIPS_REG_HI, false, true);
gpr.KillImmediate(MIPS_REG_LO, false, true);
gpr.KillImmediate(rt, true, false);
// Mul, this must be EAX!
MOV(32, R(EAX), gpr.R(rs));
IMUL(32, gpr.R(rt));
MOV(32, gpr.R(MIPS_REG_HI), R(EDX));
Core/MIPS/x86/CompFPU.cpp
+13 -13
View File
@@ -231,17 +231,17 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
}
if (setMXCSR != -1) {
STMXCSR(M(&mxcsrTemp));
MOV(32, R(EAX), M(&mxcsrTemp));
AND(32, R(EAX), Imm32(~(3 << 13)));
OR(32, R(EAX), Imm32(setMXCSR << 13));
MOV(32, M(&mips_->temp), R(EAX));
MOV(32, R(TEMPREG), M(&mxcsrTemp));
AND(32, R(TEMPREG), Imm32(~(3 << 13)));
OR(32, R(TEMPREG), Imm32(setMXCSR << 13));
MOV(32, M(&mips_->temp), R(TEMPREG));
LDMXCSR(M(&mips_->temp));
}
(this->*conv)(EAX, fpr.R(fs));
(this->*conv)(TEMPREG, fpr.R(fs));
// Did we get an indefinite integer value?
CMP(32, R(EAX), Imm32(0x80000000));
CMP(32, R(TEMPREG), Imm32(0x80000000));
FixupBranch skip = J_CC(CC_NE);
MOVSS(XMM0, fpr.R(fs));
XORPS(XMM1, R(XMM1));
@@ -249,12 +249,12 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
// At this point, -inf = 0xffffffff, inf/nan = 0x00000000.
// We want -inf to be 0x80000000 inf/nan to be 0x7fffffff, so we flip those bits.
MOVD_xmm(R(EAX), XMM0);
XOR(32, R(EAX), Imm32(0x7fffffff));
MOVD_xmm(R(TEMPREG), XMM0);
XOR(32, R(TEMPREG), Imm32(0x7fffffff));
SetJumpTarget(skip);
fpr.DiscardR(fd);
MOV(32, fpr.R(fd), R(EAX));
MOV(32, fpr.R(fd), R(TEMPREG));
if (setMXCSR != -1) {
LDMXCSR(M(&mxcsrTemp));
@@ -371,10 +371,10 @@ void Jit::Comp_mxc1(MIPSOpcode op) {
}
} else {
AND(32, gpr.R(rt), Imm32(~(1 << 23)));
MOV(32, R(EAX), gpr.R(MIPS_REG_FPCOND));
AND(32, R(EAX), Imm32(1));
SHL(32, R(EAX), Imm8(23));
OR(32, gpr.R(rt), R(EAX));
MOV(32, R(TEMPREG), gpr.R(MIPS_REG_FPCOND));
AND(32, R(TEMPREG), Imm32(1));
SHL(32, R(TEMPREG), Imm8(23));
OR(32, gpr.R(rt), R(TEMPREG));
}
gpr.UnlockAll();
} else if (fs == 0) {
Core/MIPS/x86/CompVFPU.cpp
+21 -21
View File
@@ -1094,17 +1094,17 @@ void Jit::Comp_Vcmp(MIPSOpcode op) {
ANDPS(XMM0, M(vcmpMask[n - 1]));
MOVAPS(M(vcmpResult), XMM0);
MOV(32, R(EAX), M(&vcmpResult[0]));
MOV(32, R(TEMPREG), M(&vcmpResult[0]));
for (int i = 1; i < n; ++i) {
OR(32, R(EAX), M(&vcmpResult[i]));
OR(32, R(TEMPREG), M(&vcmpResult[i]));
}
// Aggregate the bits. Urgh, expensive. Can optimize for the case of one comparison,
// which is the most common after all.
CMP(32, R(EAX), Imm8(affected_bits & 0x1F));
CMP(32, R(TEMPREG), Imm8(affected_bits & 0x1F));
SETcc(CC_E, R(ECX));
SHL(32, R(ECX), Imm8(5));
OR(32, R(EAX), R(ECX));
OR(32, R(TEMPREG), R(ECX));
} else {
// Finalize the comparison for ES/NS.
if (cond == VC_ES || cond == VC_NS) {
@@ -1113,17 +1113,17 @@ void Jit::Comp_Vcmp(MIPSOpcode op) {
// It's inversed below for NS.
}
MOVD_xmm(R(EAX), XMM0);
MOVD_xmm(R(TEMPREG), XMM0);
if (inverse) {
XOR(32, R(EAX), Imm32(0xFFFFFFFF));
XOR(32, R(TEMPREG), Imm32(0xFFFFFFFF));
}
AND(32, R(EAX), Imm32(0x31));
AND(32, R(TEMPREG), Imm32(0x31));
}
gpr.UnlockAllX();
gpr.MapReg(MIPS_REG_VFPUCC, true, true);
AND(32, gpr.R(MIPS_REG_VFPUCC), Imm32(~affected_bits));
OR(32, gpr.R(MIPS_REG_VFPUCC), R(EAX));
OR(32, gpr.R(MIPS_REG_VFPUCC), R(TEMPREG));
fpr.ReleaseSpillLocks();
}
@@ -1452,12 +1452,12 @@ void Jit::Comp_Vf2i(MIPSOpcode op) {
// Except for truncate, we need to update MXCSR to our preferred rounding mode.
if (setMXCSR != -1) {
STMXCSR(M(&mxcsrTemp));
MOV(32, R(EAX), M(&mxcsrTemp));
AND(32, R(EAX), Imm32(~(3 << 13)));
MOV(32, R(TEMPREG), M(&mxcsrTemp));
AND(32, R(TEMPREG), Imm32(~(3 << 13)));
if (setMXCSR != 0) {
OR(32, R(EAX), Imm32(setMXCSR << 13));
OR(32, R(TEMPREG), Imm32(setMXCSR << 13));
}
MOV(32, M(&mips_->temp), R(EAX));
MOV(32, M(&mips_->temp), R(TEMPREG));
LDMXCSR(M(&mips_->temp));
}
@@ -1490,12 +1490,12 @@ void Jit::Comp_Vf2i(MIPSOpcode op) {
MAXSD(XMM0, M(&minIntAsDouble));
// We've set the rounding mode above, so this part's easy.
switch ((op >> 21) & 0x1f) {
case 16: CVTSD2SI(EAX, R(XMM0)); break; //n
case 17: CVTTSD2SI(EAX, R(XMM0)); break; //z - truncate
case 18: CVTSD2SI(EAX, R(XMM0)); break; //u
case 19: CVTSD2SI(EAX, R(XMM0)); break; //d
case 16: CVTSD2SI(TEMPREG, R(XMM0)); break; //n
case 17: CVTTSD2SI(TEMPREG, R(XMM0)); break; //z - truncate
case 18: CVTSD2SI(TEMPREG, R(XMM0)); break; //u
case 19: CVTSD2SI(TEMPREG, R(XMM0)); break; //d
}
MOVD_xmm(fpr.VX(tempregs[i]), R(EAX));
MOVD_xmm(fpr.VX(tempregs[i]), R(TEMPREG));
}
for (int i = 0; i < n; ++i) {
@@ -2471,9 +2471,9 @@ void Jit::Comp_Viim(MIPSOpcode op) {
s32 imm = (s32)(s16)(u16)(op & 0xFFFF);
FP32 fp;
fp.f = (float)imm;
MOV(32, R(EAX), Imm32(fp.u));
MOV(32, R(TEMPREG), Imm32(fp.u));
fpr.MapRegV(dreg, MAP_DIRTY | MAP_NOINIT);
MOVD_xmm(fpr.VX(dreg), R(EAX));
MOVD_xmm(fpr.VX(dreg), R(TEMPREG));
ApplyPrefixD(&dreg, V_Single);
fpr.ReleaseSpillLocks();
@@ -2491,9 +2491,9 @@ void Jit::Comp_Vfim(MIPSOpcode op) {
FP16 half;
half.u = op & 0xFFFF;
FP32 fval = half_to_float_fast5(half);
MOV(32, R(EAX), Imm32(fval.u));
MOV(32, R(TEMPREG), Imm32(fval.u));
fpr.MapRegV(dreg, MAP_DIRTY | MAP_NOINIT);
MOVD_xmm(fpr.VX(dreg), R(EAX));
MOVD_xmm(fpr.VX(dreg), R(TEMPREG));
ApplyPrefixD(&dreg, V_Single);
fpr.ReleaseSpillLocks();
Core/MIPS/x86/RegCache.h
+3
View File
@@ -37,6 +37,9 @@ using namespace Gen;
#define CTXREG EBP
#endif
// This must be one of EAX, EBX, ECX, EDX as they have 8-bit subregisters.
#define TEMPREG EAX
struct MIPSCachedReg {
OpArg location;
bool away; // value not in source register