e01ca5b057
Logging API change (refactor) ( #19324 )
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* Rename LogType to Log
* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.
* Mac/ARM64 buildfix
* Do the same with the hle result log macros
* Rename the log names to mixed case while at it.
* iOS buildfix
* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
88b6442527
irjit: Add facility for native reg transfer.
2023-09-24 16:28:29 -07:00
2f300c2023
Merge pull request #18060 from unknownbrackets/x86-jitbase
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x86jit: Bake emuhack mask into jitbase
2023-09-03 22:53:23 +02:00
1d152a1486
x86jit: Bake emuhack mask into jitbase.
2023-09-03 12:49:36 -07:00
1b756ff8c1
arm64jit: Add initial base for IR jit.
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This works, but very slowly at this point.
2023-09-03 12:14:28 -07:00
4b1c809886
x86jit: Implement a few more float ops, shuffle.
2023-08-27 23:24:30 -07:00
07fa1ed573
x86jit: Automatically flush incompatible regs.
2023-08-21 21:16:54 -07:00
db34b85107
irjit: Allow flag-based allocation order.
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Sometimes backends have needs, like XMM0/v0-only, or similar.
2023-08-21 20:46:05 -07:00
36b6aa4728
riscv: Allow GPR "SIMD" without FPR SIMD.
2023-08-20 12:42:11 -07:00
6a75e6712e
riscv: Use automapping for special cases too.
2023-08-20 12:42:11 -07:00
a190793ad2
riscv: Simplify mapping for more instructions.
2023-08-20 12:42:11 -07:00
cc4bc406d5
riscv: Cleanup VfpuCtrlToReg meta, use auto-map.
2023-08-20 12:42:11 -07:00
e40ae60029
riscv: Mark normalized32 after mapping.
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It's less confusing to separate it.
2023-08-20 12:42:11 -07:00
f9bf7de701
riscv: Use a single reg cache.
2023-08-20 12:42:11 -07:00
e30fb82a64
riscv: Remove some unused reg funcs.
2023-08-20 12:42:11 -07:00
a23ade8f75
riscv: Map IR regs based on metadata.
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Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
2023-08-20 12:42:11 -07:00
161465ab66
riscv: Centralize register FlushAll().
2023-08-19 21:30:03 -07:00
f3d4bd8c11
riscv: Centralize reg-as-pointer.
2023-08-19 21:24:36 -07:00
92f7374c89
riscv: Centralize reg mapping itself.
2023-08-19 16:15:49 -07:00
718a1b3944
riscv: Centralize MarkDirty flagging.
2023-08-19 16:15:49 -07:00
4e41f83ecc
riscv: Centralize IR reg cache metadata checks.
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These are all largely the same between backends.
2023-08-17 23:03:31 -07:00
ebab0e1591
riscv: Centralize reg allocation.
2023-08-17 18:50:33 -07:00
b30daa5760
riscv: Centralize state of regcaches.
2023-08-15 21:51:38 -07:00
b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit
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riscv: Spill registers more intelligently
2023-07-30 14:49:37 -07:00
f870271011
riscv: Spill registers more intelligently.
2023-07-30 14:24:12 -07:00
5ef4b2b5fa
riscv: Fix assert when flushing not mapped reg.
2023-07-30 14:19:28 -07:00
c24e3ef831
riscv: Implement ll/sc.
2023-07-30 00:45:51 -07:00
067a033dc0
riscv: Add FPU regcache.
2023-07-25 20:33:56 -07:00
b97b7f3663
riscv: Make some regcache methods private.
2023-07-25 19:42:04 -07:00
b6f83ca969
riscv: Cleanup some pointerification flags.
2023-07-23 21:17:55 -07:00
2c7da94bd1
riscv: Implement shifts and compares.
2023-07-23 18:01:00 -07:00
94be343591
riscv: Try to keep regs normalized, track.
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Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
2023-07-23 18:01:00 -07:00
8ee73264bf
riscv: Correct depointerify on FlushAll().
2023-07-23 18:01:00 -07:00
720f868a10
riscv: Use R_RA as a temporary for calls.
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This is the most logical thing, since we're about to write it anyway.
2023-07-23 18:01:00 -07:00
d31eded9ba
riscv: Allow dirty pointers, explicitly.
2023-07-23 18:01:00 -07:00
165169eb31
riscv: Implement load and store ops.
2023-07-23 18:01:00 -07:00
c6c25af484
riscv: Add some safety to pointerifying.
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We have to clear the upper bits in case of sign extension or other things.
2023-07-23 18:01:00 -07:00
4c1cc2dfdc
riscv: Add a register cache for jit.
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Not yet actually used. Might be buggy.
2023-07-23 18:01:00 -07:00
Henrik Rydgård