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https-linux-poc
Commit Graph
3004 Commits
Author SHA1 Message Date
Henrik Rydgard b5ee47a80c x86 jit: SIMD-ify lv.q and sv.q 2014-11-25 23:28:29 +01:00
Henrik Rydgård 4db6b7f3e2 SIMD-ify a couple instructions a bit 2014-11-25 22:47:26 +01:00
Kingcom f6cedcbff5 Replace assembler with a submodule 2014-11-23 21:09:40 +01:00
Unknown W. Brackets a4b9122943 x86jit: Use NS instead of NBE for checked entries. 
This may cause us to more correctly bail on linked blocks in some cases.
 2014-11-23 11:05:49 -08:00
Unknown W. Brackets fe525a52f9 Update native (shutdown crash) + comment. 2014-11-23 11:04:07 -08:00
Unknown W. Brackets 473f388088 Disable the simd stuff for now. 
Won't have time to look at this for a bit...
 2014-11-20 14:07:56 -08:00
xSacha 88b1c00a67 MIPS: Complete MIPSX rename for buildfix. 2014-11-19 07:55:44 +10:00
Henrik Rydgård 6a49337a0c Merge pull request #7096 from unknownbrackets/jit-simd 
x86jit: Add basic support for mapping SIMD
 2014-11-18 18:25:39 +01:00
SachaandUnknown W. Brackets 65e008f053 Implement a MipsJit. 2014-11-18 08:40:57 -08:00
xSachaandUnknown W. Brackets 3172fa22e2 Integrate new MIPS emitter. 2014-11-18 08:40:57 -08:00
Unknown W. Brackets ab7dd0df25 x86jit: Add an option to enable/disable vpfu simd. 2014-11-17 20:37:27 -08:00
Henrik Rydgard 53b5d331b4 Assorted minor optimizations 2014-11-17 21:21:44 +01:00
Henrik Rydgard 3298c1143f Arm disasm: Coalesce multiple "BKPT 1" like we do on x86 for INT 3 2014-11-17 21:21:44 +01:00
Henrik Rydgard 74d8a9bdba Clean up after the block linker. armdis: add BKPT 2014-11-17 21:21:34 +01:00
Unknown W. Brackets 921b39ebf5 x86jit: Optimize a 2-reg simd load. 2014-11-16 15:05:17 -08:00
Unknown W. Brackets e68eb0a292 x86jit: Load sequential regs in one shot. 2014-11-16 15:05:17 -08:00
Unknown W. Brackets ed501302a2 x86jit: Add a check to see if we can map simd. 2014-11-16 15:05:16 -08:00
Unknown W. Brackets 27148d3712 x86jit: Add some helpers to check state. 2014-11-16 13:33:16 -08:00
Unknown W. Brackets de566be2ce x86jit: Split out the logic for loading simd regs. 2014-11-16 13:33:15 -08:00
Unknown W. Brackets 5347431c20 x86jit: Initial simd for VecDo3(). Broken. 
I'm not sure why/where it's broken...
 2014-11-16 13:33:15 -08:00
Unknown W. Brackets aad505e7b3 x86jit: Add a TryMapDirtyInInVS() for 3-op. 2014-11-16 13:33:14 -08:00
Unknown W. Brackets 88a753eff3 x86jit: Add an invariant contract to the fpu cache. 
This should help catch things better in debug mode.
 2014-11-16 13:33:14 -08:00
Unknown W. Brackets 39afeb490f x86jit: Add some typesafety. 2014-11-16 13:33:13 -08:00
Unknown W. Brackets 4335bf3346 x86jit: Add basic mapping of SIMD regs. 
Not tested yet, just sketched out.  All very suboptimal.
 2014-11-16 13:33:13 -08:00
Unknown W. Brackets 9429359b47 x86jit: Add fallbacks when moving from VS -> V. 2014-11-16 13:33:12 -08:00
Unknown W. Brackets 2862367927 x86jit: Add force-non-simd to all current ops. 
Unless they already use MapRegs, because that will automatically handle
it.
 2014-11-16 13:33:12 -08:00
Unknown W. Brackets 4cf0913692 x86jit: Sketch some initial SIMD apis. 2014-11-16 13:33:07 -08:00
Henrik Rydgard e43c7af32c ARM Jit: Implement quaternion multiplication 2014-11-16 19:12:00 +01:00
Henrik Rydgard bfcd3690b6 x86 jit: Fix+enable quaternion product, optimize "sw zero, *" 2014-11-16 18:37:38 +01:00
Henrik Rydgard 28ca8d4818 x86 jit: Use LEA to emulate addu but only when it can save a few bytes 2014-11-16 17:39:47 +01:00
Henrik Rydgard 1c78e29c79 x86 jit: For clarity, use TEMPREG where it doesn't matter that it's EAX. 
Might have missed a few places.
 2014-11-16 17:38:26 +01:00
Henrik Rydgard 8b90f881b8 x86 jit: A tiny optimization and a tiny bugfix 2014-11-16 16:46:35 +01:00
xSacha 57e4088216 Introduce fake vertex decoder JIT as well. 
Compiles and links on CI20 but gets unknown crash in GL driver.
 2014-11-13 17:10:29 +10:00
Sacha c421617c84 Fix Qt build by building Arm disassembler for all platforms. 2014-11-13 00:55:00 +10:00
Sacha a0086f6412 Introduce a Fake JIT for generic builds. 2014-11-13 00:09:51 +10:00
Kingcom 479c8646a2 Change vpfxs/r/t disassembly syntax 2014-11-12 00:09:57 +01:00
Unknown W. Brackets 096b41cceb x86jit: Interleave reg usage in vcmp. 2014-11-10 23:22:04 -08:00
Unknown W. Brackets 0e1aa35e84 x86jit: Just do the ES/NS compare once. 2014-11-10 23:04:38 -08:00
Unknown W. Brackets 2758e8fa3c x86jit: Optimize vcmp for single and simd. 2014-11-10 23:04:37 -08:00
Unknown W. Brackets 94e29da6c4 Fix a typo in the mips assembler. 
Oops, this should be a unique value of course.
 2014-11-10 09:13:11 -08:00
Unknown W. Brackets 01c2b88911 Avoid signed ints, seems to cause clang errors. 2014-11-09 16:49:24 -08:00
Henrik Rydgård 7fbe8ba898 Merge pull request #7076 from unknownbrackets/debugger 
Add VFPU instructions to the mips asm tables
 2014-11-10 00:57:08 +01:00
Unknown W. Brackets 370fb86379 Add VFPU instructions to the mips asm tables. 2014-11-09 15:14:07 -08:00
Unknown W. Brackets 86e3739a3e x86jit: Optimize some cases of ins/ext. 
They happen but are minor.
 2014-11-09 09:22:29 -08:00
Unknown W. Brackets e05263af32 x86jit: Allow EBX sign extension for 32-bit. 2014-11-09 09:07:52 -08:00
Unknown W. Brackets 8dbd3c3b9c x86jit: Don't lie about ZERO when it's not an imm. 2014-11-09 08:27:02 -08:00
Unknown W. Brackets d0a2ced2f9 x86jit: Flip cc in stl* to avoid reg loads. 
Unfortunately, this zero thing is now concerning me...
 2014-11-09 08:15:39 -08:00
Unknown W. Brackets 59f491eddb x86jit: Micro optimize slt* a bit. 
This improves their performance and hopefully latency.  It also avoids
filling registers that are not likely to be used again.

Fixed a small mistake.
 2014-11-09 07:23:44 -08:00
Henrik Rydgard 18495a452d Rename an enum 2014-11-09 14:55:23 +01:00
Henrik Rydgard a19d0b648a x86 jit: Add a simple speedhack (ignore masking stack pointers) but disable due to low impact. 2014-11-09 14:54:39 +01:00