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3004 Commits
Author SHA1 Message Date
Unknown W. BracketsandGitHub 510daa664f interp: Correct vsbn instruction. 
Accidentally broken in f2be0cb.  Rarely used.
 2019-07-07 22:58:54 -07:00
Unknown W. Brackets 732d344328 Common: Fix some unused ident and case warnings. 2019-06-22 13:22:12 -07:00
Henrik Rydgård a0dc85a9d7 Fix a bunch of inconsequential uninitialized variables 2019-06-18 00:18:40 +02:00
Henrik Rydgård 379113680c Fix static analysis warning about access outside array (d[ins] = s[ins * 4] * t[0]) 2019-06-18 00:17:43 +02:00
Unknown W. Brackets 3cb1c33fd9 interp: Fix dumb mistake in vtfm. 
Had done final testing on this with a 2x2 matrix because it was simpler...

Fixes #12109.
 2019-06-16 18:29:29 -07:00
Henrik Rydgård 30831f3ea1 Implement and test clz32, use it in the MIPS interpreter cores. 
This will be useful for our vfpu-dot implementations later.
 2019-06-14 18:39:15 +02:00
Henrik Rydgård f49999efca Revert "ARM64 vmmul experiment: Disable if S and T matrices overlap." 
This reverts commit c4d26dcb10.
 2019-06-06 09:34:23 +02:00
Henrik Rydgård 649b7a5671 ARM64 vmmov experiment: Reduce precision by using FMUL+FADD instead of FMADD. May help #12082 and thus also #11179 and #9843. 2019-06-05 00:02:32 +02:00
Henrik Rydgård c4d26dcb10 ARM64 vmmul experiment: Disable if S and T matrices overlap. 
If this fixes anything in #12082, we have a regalloc bug I guess...
 2019-06-04 22:24:19 +02:00
Henrik Rydgård 7853c90abb JIT: Split VFPU_MTX disable options. To help with #9843 2019-06-03 23:28:15 +02:00
Unknown W. Brackets c773359095 arm64jit: Tweak matrix vfpu overlap detect, etc. 
Tried making changes to them to guess at issues for #9843, but didn't find
any.  Still, I think these changes are worthwhile, if small.
 2019-06-02 22:10:20 -07:00
Unknown W. Brackets b4137b2403 armjit: Fix avoidLoad handling for fpu regs. 2019-06-02 22:03:26 -07:00
Unknown W. Brackets 1358a80aa6 arm64jit: Fix avoidLoad handling for fpu regs. 2019-06-02 22:03:06 -07:00
Unknown W. Brackets 816abce8fc Windows: Fix some warnings. 
Also one in armjit.
 2019-06-02 09:30:38 -07:00
Henrik Rydgård f4e489ee50 Fix minor oversight 2019-06-02 17:49:21 +02:00
Henrik Rydgård 55b4b4b9e3 Style fix 2019-06-02 16:22:19 +02:00
Henrik Rydgård 6fd40332fd JitDisable: Add option to disable regalloc across instructions (flush after every instruction) 2019-06-02 16:06:10 +02:00
Henrik Rydgård 2f26297062 Clean up some more ifdefs 2019-05-10 23:25:57 +02:00
driver1998 5072584781 Fix neon headers for MSVC ARM64 
MSVC uses arm64_neon.h for ARM64, arm_neon.h is ARM32 only.
 2019-05-04 22:45:15 +08:00
M4xw b9352354c9 Masked PSP Memory support for the AArch64 Dynarec 2019-04-15 12:07:57 +02:00
Unknown W. Brackets ec7cffa847 interp: Handle vtfm/vhtfm prefixes properly. 2019-04-02 18:46:39 -07:00
Unknown W. Brackets 442d6450bb interp: Correct prefixes on vfad and vavg. 
Including write mask, which didn't work before.
 2019-04-02 18:46:39 -07:00
Unknown W. Brackets 5414c12a15 interp: Cleanup prefix/size in vcrsp/vqmul. 2019-04-02 07:12:34 -07:00
Unknown W. Brackets 58573cd4b4 interp: Handle invalid swizzle for vmin/vmax. 2019-04-02 07:08:33 -07:00
Unknown W. Brackets e8c060bb5f interp: Correct vwbn and vlgb size behavior. 2019-04-02 07:08:20 -07:00
Unknown W. Brackets 89dbfd7d5b interp: Better prefixes for vdiv/similar ops. 
Turns out it does work, just uses the wrong slot like S/T after all.
These other ops must go through the a similar process.
 2019-04-02 07:07:53 -07:00
Henrik RydgårdandGitHub 24cfad87d1 Merge pull request #11955 from unknownbrackets/vfpu-chunk6 
Correct prefixes for several swizzled ops, use zero for invalid
 2019-04-01 17:13:34 +02:00
Henrik RydgårdandGitHub b346142df8 Merge pull request #11954 from unknownbrackets/vfpu-chunk5 
Fix prefix and size handling for vsbx, vsocp, and integer conv ops
 2019-04-01 17:12:03 +02:00
Unknown W. Brackets 6f87987e7b interp: Correct prefixes on vdot/vhdp. 2019-03-31 17:12:21 -07:00
Unknown W. Brackets b24f84d1a2 interp: Handle prefixes on matrix init ops. 2019-03-31 17:11:24 -07:00
Unknown W. Brackets 59905de719 interp: Correct vsgn out of swizzle bounds. 2019-03-31 17:10:51 -07:00
Unknown W. Brackets 85ff32eed1 interp: Handle vsgn prefixing. 
One could compare against 3 using this, it just generates zeros to compare
with.
 2019-03-31 17:10:51 -07:00
Unknown W. Brackets a5214d0b1a Jit: Ignore high bit in vmfvc/vmtvc. 2019-03-31 17:09:55 -07:00
Unknown W. Brackets b881a689c4 interp: Ignore high bit in vmfvc/vmtvc. 
Both 0 and 128 read/write the S prefix, for example.
 2019-03-31 17:09:55 -07:00
Unknown W. Brackets dffa238611 interp: Handle invalid swizzle in vsge/vslt. 2019-03-31 15:05:43 -07:00
Unknown W. Brackets dfd8094f21 interp: Implement vcrs prefixes and sizes. 
It only makes sense as triple, but it can be used as quad/single/etc. and
has consistent and sane results.
 2019-03-31 15:05:15 -07:00
Unknown W. Brackets fa7ac7bc64 interp: Correct simple vmov variant prefixing. 2019-03-31 15:01:28 -07:00
Unknown W. Brackets 01aebe54b9 interp: Correct vdet prefix handling. 2019-03-31 15:01:11 -07:00
Unknown W. Brackets cc58d0d3a3 interp: Correct prefixes in vsrt ops. 2019-03-31 15:00:12 -07:00
Unknown W. Brackets f2be0cb083 interp: Correct prefixes for vsbn/vsbz. 2019-03-31 13:52:59 -07:00
Unknown W. Brackets 175ceef583 interp: Cleanup vsocp size handling. 2019-03-31 13:52:07 -07:00
Unknown W. Brackets 4a2f8a74dc interp: Correct size handling for vi2x ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets b75690787e interp: Correct swizzle on vx2i ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets 68cdcba6c5 interp: Don't write lane 2 on single colorconv. 
Not that it's valid to use the op with that size anyway.
 2019-03-31 13:51:12 -07:00
Unknown W. Brackets 5736b1be2a interp: Correct some negative invalid zero cases. 
In these cases, the input value wires to +0.  Also, transposed the values
in a comment (oops.)
 2019-03-31 13:45:37 -07:00
Unknown W. Brackets aa998b815c interp: Force vscmp result of invalid to zero. 
Some other ops do this, but mostly only that do plus or minus.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets c7e83cd4fa interp: Correct vfim for -inf and similar. 
Was dropping the sign bit before for inf and nan.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets 5749ae09d0 interp: Correct vmfvc register behavior. 
The target and source registers were completely wrong.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets b2e024025f interp: Handle wrong sizes of vf2h/vh2f. 
Probably not ever used, but they have consistent behavior.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets aceb0a8244 interp: Correct vrnd prefix handling. 
We don't match random values perfectly anyway, but at least we should vary
at the right times.
 2019-03-31 13:41:48 -07:00