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94 Commits
Author SHA1 Message Date
Unknown W. Brackets bbeb5758b7 x86jit: Simplify VS() / VSX() usage. 2014-11-27 00:07:17 -08:00
Unknown W. Brackets 039510a3e3 x86jit: Respect dirty even for non-simd. 2014-11-26 23:29:20 -08:00
Unknown W. Brackets f63c165f64 x86jit: Fix several cases of missing dirty checks. 2014-11-26 23:28:14 -08:00
Henrik Rydgard becdb14a3f x86 jit: Fix a couple issues in simd storefromregister 2014-11-26 22:25:18 +01:00
Henrik Rydgård 80797dc723 Merge pull request #7108 from unknownbrackets/jit-simd 
Fix the simd issue at least for Wipeout
 2014-11-26 21:42:02 +01:00
Unknown W. Brackets e5dabaabe2 x86jit: Optimize simd->non for 1-lane a little. 2014-11-26 09:20:50 -08:00
Unknown W. Brackets 5d0c32d1e6 x86jit: Assume non-simd regs are dirty. 2014-11-26 09:19:50 -08:00
Henrik Rydgard 804de50711 x86 jit: SIMD-ify VFPU register file writebacks where possible 2014-11-26 01:33:05 +01:00
Henrik Rydgard b3c8a82c49 x86 jit: SIMD-ify some more 2014-11-25 23:56:46 +01:00
Unknown W. Brackets ab7dd0df25 x86jit: Add an option to enable/disable vpfu simd. 2014-11-17 20:37:27 -08:00
Unknown W. Brackets 921b39ebf5 x86jit: Optimize a 2-reg simd load. 2014-11-16 15:05:17 -08:00
Unknown W. Brackets e68eb0a292 x86jit: Load sequential regs in one shot. 2014-11-16 15:05:17 -08:00
Unknown W. Brackets ed501302a2 x86jit: Add a check to see if we can map simd. 2014-11-16 15:05:16 -08:00
Unknown W. Brackets 27148d3712 x86jit: Add some helpers to check state. 2014-11-16 13:33:16 -08:00
Unknown W. Brackets de566be2ce x86jit: Split out the logic for loading simd regs. 2014-11-16 13:33:15 -08:00
Unknown W. Brackets 5347431c20 x86jit: Initial simd for VecDo3(). Broken. 
I'm not sure why/where it's broken...
 2014-11-16 13:33:15 -08:00
Unknown W. Brackets aad505e7b3 x86jit: Add a TryMapDirtyInInVS() for 3-op. 2014-11-16 13:33:14 -08:00
Unknown W. Brackets 88a753eff3 x86jit: Add an invariant contract to the fpu cache. 
This should help catch things better in debug mode.
 2014-11-16 13:33:14 -08:00
Unknown W. Brackets 4335bf3346 x86jit: Add basic mapping of SIMD regs. 
Not tested yet, just sketched out.  All very suboptimal.
 2014-11-16 13:33:13 -08:00
Unknown W. Brackets 9429359b47 x86jit: Add fallbacks when moving from VS -> V. 2014-11-16 13:33:12 -08:00
Unknown W. Brackets 2862367927 x86jit: Add force-non-simd to all current ops. 
Unless they already use MapRegs, because that will automatically handle
it.
 2014-11-16 13:33:12 -08:00
Unknown W. Brackets 4cf0913692 x86jit: Sketch some initial SIMD apis. 2014-11-16 13:33:07 -08:00
Henrik Rydgård eab010a0c0 x86 JIT: Sacrifice a register for a pointer to the MIPS context. Shrinks emitted x86 code considerably. 
Nice in 64-bit, but might be a bit too much in 32-bit though... Needs testing.
 2014-10-12 19:35:55 +02:00
Unknown W. Brackets 3001866d18 Skip flushing FPU/VFPU regs if none were allocated. 
They're not used as often, so this usually saves time.  About 1% during
tests.
 2014-03-30 00:42:25 -07:00
The Dax 21ce99cabd Fix Unix-like builds. 2014-03-15 10:02:47 -04:00
Henrik Rydgard f9f6e9492d Reorder vfpu data in saved kernel contexts when loading in a new version. 2013-11-28 13:27:51 +01:00
Henrik Rydgard 55500d4bb6 Reorder VFPU registers in memory so that we can flush and reload them in bulk more often. 
Doesn't actually do that yet, that's for the NEON branch.
 2013-11-28 13:27:51 +01:00
Henrik Rydgard 5ad04a23f4 x86 jit: Rename BindToRegister to MapReg 2013-11-09 15:23:31 +01:00
Unknown W. Brackets 95c68ae1e7 Assert some unlikely buffer overflows. 2013-10-26 18:30:55 -07:00
Unknown W. Brackets e8091dce44 Speed up FPURegCache::Start() on x86. 
This cuts that func by 97% when running the automated tests, and it was 8%
of the total time.  Won't really affect games.
 2013-10-24 08:27:42 -07:00
Unknown W. Brackets 2751da1cec Cut down on work in regcache init on x86. 
Very tiny tiny optimization for games, but 8-10% optimization for tests.
 2013-09-19 00:29:50 -07:00
Henrik Rydgard 324cde5a79 Let's actually use the log category mechanism. A first step. 2013-09-07 21:19:21 +02:00
Unknown W. Brackets 64c2ea86c0 Add a method to save the gpr/fpr state in jit. 2013-08-16 00:12:49 -07:00
Unknown W. Brackets 64c42ffaf2 Fix some warnings generated by clang. 2013-02-24 10:23:31 -08:00
Unknown W. Brackets 0bfc380575 Try to reuse temp regs for better caching. 2013-02-18 00:32:42 -08:00
Unknown W. Brackets 18c03d0816 Handle temp regs better, no need for direct access. 2013-02-18 00:11:57 -08:00
Unknown W. Brackets 08a42a1aaf Preserve orig regs when applying vfpu prefixes. 2013-02-17 22:37:56 -08:00
Unknown W. Brackets d63548799b Add more temp regs, allow swapping if necessary. 2013-02-17 22:18:46 -08:00
Unknown W. Brackets 0bd382c518 Discard temp regs right away, some helper funcs. 2013-02-16 10:18:13 -08:00
Unknown W. Brackets 35537b3c97 Add TEMP0 fpu regs to x86 like in armjit. 
But... will probably need more and the ability to swap into memory
if we want to deal with prefixes.
 2013-02-16 03:27:03 -08:00
Henrik Rydgard 78923f5538 Jit a little more (vfpu single load/store, transfer instructions) 2013-02-10 12:14:55 +01:00
Lewis Robbins 442e64cd84 compiler warning and const top-level const 2013-02-05 17:54:29 +00:00
Henrik Rydgard 2738417040 VFPU JIT: start setting up infrastructure. very incomplete. vdot works if undisabled, but isn't complete. 2013-01-26 01:34:19 +01:00
Henrik Rydgard 68991511ee Split out the FPU reg cache into its own file too. 2013-01-26 01:34:19 +01:00