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54 Commits
Author SHA1 Message Date
Unknown W. Brackets bf7a6eb2cd riscv: Add jit for some initial instructions. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 4c1cc2dfdc riscv: Add a register cache for jit. 
Not yet actually used.  Might be buggy.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 47b81985bd riscv: Initial untested dispatcher. 
The minimum to actually, probably, running code.  Pretty slow.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets e271e43ec5 riscv: Initial staffolding for IR based jit. 2023-07-23 18:01:00 -07:00