ba148e5ec7
JIT/IRJit: Delete an old "function preloading" experiment
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This caused some confusion while trying to debug #20502
2025-06-11 15:45:18 +02:00
85e7ff7ac3
Target->Native renaming. More intuitive (at least to me)
2024-07-22 01:24:34 +02:00
9d36a08ec4
Some renaming, remove a gross hack
2024-07-21 19:12:51 +02:00
e01ca5b057
Logging API change (refactor) ( #19324 )
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* Rename LogType to Log
* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.
* Mac/ARM64 buildfix
* Do the same with the hle result log macros
* Rename the log names to mixed case while at it.
* iOS buildfix
* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
5526ef012c
Store IR instructions in a large arena vector instead of loosely in each block.
2024-06-07 09:28:27 +02:00
e75e7a0e43
Add an optimizeForInterpreter flag
2024-05-26 13:41:31 +02:00
126d88ecfc
Back out clearly inconsequential/useless .reserve() calls
2023-12-29 08:27:56 +01:00
b871e76d05
[Core/Debugger/FileLoaders/FileSystems/MIPS] Using reserve if possible
2023-12-15 13:59:19 +03:00
00c80cea6e
irjit: Optimize offset logging during compile.
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As I guessed, this was expensive. using a vector and reserve isn't very.
It's nice to keep this before logBlocks_ is > 0, in case it's set mid
block.
2023-09-30 15:56:18 -07:00
9b2fa46861
IR: Add mini native jit MIPS block profiler.
2023-09-24 23:04:29 -07:00
0faa1109d2
Included <algorithm> for std::min
2023-09-07 12:14:36 +03:00
1b756ff8c1
arm64jit: Add initial base for IR jit.
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This works, but very slowly at this point.
2023-09-03 12:14:28 -07:00
2e64abd2a0
x86jit: Improve some debug labels.
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Helps when running a profiler that reads these.
2023-08-27 12:51:29 -07:00
08ea31f405
x86jit: Improve debug disasm.
2023-08-20 22:28:54 -07:00
c491f701ba
x86jit: Add initial IR-based jit backend.
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It works, but pretty slow in some parts with everything stubbed.
2023-08-20 22:28:54 -07:00
f9bf7de701
riscv: Use a single reg cache.
2023-08-20 12:42:11 -07:00
4e41f83ecc
riscv: Centralize IR reg cache metadata checks.
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These are all largely the same between backends.
2023-08-17 23:03:31 -07:00
b30daa5760
riscv: Centralize state of regcaches.
2023-08-15 21:51:38 -07:00
2bb67db43c
riscv: Switch to the logBlocks model for disasm.
2023-08-13 10:37:21 -07:00
8c036a889d
riscv: Add debug log of block disasm.
2023-08-13 10:32:04 -07:00
fcc90095f7
riscv: Enable block linking.
2023-08-12 09:37:02 -07:00
247788806a
irjit: Add direct helper for start PC.
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It's annoying always fetching length too.
2023-08-12 09:37:02 -07:00
b3cdf06c5a
riscv: Write fixup on block invalidation.
2023-08-12 09:37:02 -07:00
3757ebca2d
irjit: Invalidate/finalize target blocks.
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Doesn't actually do anything yet, but adds plumbing.
2023-08-12 09:37:02 -07:00
4b9011e475
riscv: Reduce call bloat using temps.
2023-08-08 23:17:32 -07:00
ad4cbbab8e
riscv: Don't cache mipState on backend.
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Bad sign if we're trying to use it, anyway.
2023-08-08 23:17:32 -07:00
93e3d35f5d
irjit: Move more to IRNativeBackend, split.
2023-08-06 00:16:43 -07:00
691799a0ca
irjit: Centralize native jit compile dispatch.
2023-08-03 23:14:58 -07:00
c24dca12bb
Build: Fix link issue for rv64 disasm.
2023-07-30 16:06:55 -07:00
b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit
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riscv: Spill registers more intelligently
2023-07-30 14:49:37 -07:00
f870271011
riscv: Spill registers more intelligently.
2023-07-30 14:24:12 -07:00
45d44c1d4f
riscv: Implement block debug interface.
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This gives us the target disasm in jit compare, bloat, etc.
2023-07-30 14:21:43 -07:00
b93275bb35
Merge pull request #17800 from unknownbrackets/riscv-jit
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More RISC-V jit ops
2023-07-30 09:26:22 +02:00
180bda6f6b
Merge pull request #17799 from unknownbrackets/irjit-lsu
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Add ll/sc to IR and x86jit
2023-07-30 09:15:55 +02:00
a5671bc716
riscv: Add simple debug log of missed ops.
2023-07-30 00:02:10 -07:00
f65b6fdb20
riscv: Remove incomplete block check.
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It shouldn't be necessary and bad things would happen anyway if it did.
2023-07-29 19:02:15 -07:00
8d60c10a64
riscv: Use jit address offsets directly.
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We'll have IR able to use block number or target offset.
2023-07-29 19:02:15 -07:00
e228748449
irjit: Add FCvtScaledSW to safely scale vi2f.
2023-07-29 18:30:15 -07:00
a5a2671af3
irjit: Implement vf2ix.
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Used in LittleBigPlanet when playing intro movies.
2023-07-29 18:01:08 -07:00
df2462b1d9
irjit: Implement ll/sc.
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These occur more than I expected in LittleBigPlanet while loading.
2023-07-29 17:57:44 -07:00
5122b0c78e
riscv: Cleanup unnecessary fcr31 func.
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Don't need this, we use DYNAMIC.
2023-07-25 20:33:56 -07:00
df313bd296
riscv: Fix rounding mode setting.
2023-07-25 20:33:56 -07:00
7071884a47
riscv: Handle rounding mode and ctrl transfers.
2023-07-25 20:33:56 -07:00
067a033dc0
riscv: Add FPU regcache.
2023-07-25 20:33:56 -07:00
a8edf5fa24
riscv: Reduce bloat in jit fallbacks.
2023-07-25 19:42:04 -07:00
f7f7531500
riscv: Fix min/max normalization.
2023-07-23 18:01:00 -07:00
34bfe93ea5
riscv: Fix block lookup issues.
2023-07-23 18:01:00 -07:00
720f868a10
riscv: Use R_RA as a temporary for calls.
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This is the most logical thing, since we're about to write it anyway.
2023-07-23 18:01:00 -07:00
76e3246065
riscv: Reduce jit codesize a bit.
2023-07-23 18:01:00 -07:00
c2da7d18bb
riscv: Stub out more IR compilation categories.
2023-07-23 18:01:00 -07:00
Henrik Rydgård