5d60fa0d0d
Common: Maintain C++11 support in sign extend.
2021-01-31 08:44:02 -08:00
1b00da2f3a
Common: Sign extend w/func not chained casts.
...
Should be clearer to read and easier to get right.
2021-01-31 01:25:52 -08:00
5354459476
irjit: Update clobber flag on inst swap.
...
Fixes IR in Persona 3.
2021-01-10 16:41:45 -08:00
9dcb70d502
irjit: Add disable flag for simplify passes.
2021-01-10 14:50:32 -08:00
4d3ec20082
ByteSwap.h results in a file name collision on some systems with byteswap.h. Fix this by merging it into BitSet.h.
2020-09-30 00:09:13 +02:00
40ec0d8358
Finish getting rid of basictypes.h
2020-09-29 15:51:51 +02:00
3162f30158
Merge base/basictypes.h into Common/Common.h (mostly).
2020-09-29 15:51:51 +02:00
f01e06aefd
irjit: Improve multiple lwr in a row.
2018-01-07 21:06:02 -08:00
fbeedd333b
irjit: Swap moves when it may allow clobbering.
...
Example:
addiu a0, a1, a2
mov s0, a0
addiu a0, a2, a3
By swapping the mov, we can eliminate it.
Only going one back because it's common and didn't want to track reads.
2018-01-07 21:06:02 -08:00
d27e428659
irjit: Convert lwr and friends to easier code.
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This makes it easier to write a (working) jit backend from IR, since these
ops are always annoying to get right.
2018-01-07 21:06:00 -08:00
b11f00cead
irjit: Combine lwl/lwr and swl/swr, like before.
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Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
2018-01-07 21:05:58 -08:00
c6d690e9b8
irjit: Handle Left/Right ops in passes.
2018-01-07 21:05:57 -08:00
cd3f4881a5
irjit: Optimize out temp lhs copies.
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Common example:
li v0, 1
beq s2, v0, somewhere
li v0, 2
Which was copying s2 before. This pattern generally doesn't happen in
MIPS code, though, so really only catches that (very common) case.
2018-01-07 12:11:16 -08:00
cffb2d61a7
irjit: Embed constant inside IRInst.
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This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
2018-01-03 23:24:04 -08:00
b37ba9e599
irjit: Add options for compile/optimize steps.
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This way the backend can set flags for the type of IR it wants. It's
seems too complex to combine certain things like lwl/lwr in a pass.
2018-01-01 08:38:12 -08:00
671be24105
irjit: Add extra temps to make lwl/swl/etc. easier.
2018-01-01 08:38:11 -08:00
5d5f10d956
Attempts to counter crashes seen in the Google Play developer console
2016-12-01 22:07:03 +01:00
4578c3cb54
jit-ir: Implement memory breakpoints.
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These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
2016-07-02 16:38:30 -07:00
a450a79f52
jit-ir: Optimize loads to transfers if possible.
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These (especially float <-> gpr) happen in all games, but gpr->gpr is
especially common in some minis. Good to reduce bloat.
2016-05-29 18:34:41 -07:00
ee31f09b67
Buildfix.
2016-05-18 07:12:21 -07:00
5534fba72c
jit-ir: Add load/store reorder and merge passes.
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Can do more in merge, potentially. Maybe it's not useful...
2016-05-17 21:24:13 -07:00
dc772e6f3a
Add missing cases to simplify pass
2016-05-15 23:39:42 +02:00
f544364c4a
Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm
2016-05-15 23:35:33 +02:00
6413b44434
jit-ir: Enable IR for madd(u)/msub(u).
2016-05-14 19:23:51 -07:00
4ac773e8b4
jit-ir: Implement bit reverse instruction.
2016-05-14 18:21:42 -07:00
0541fe36df
Symbian buildfix, fix for fpu test
2016-05-14 15:26:43 +02:00
91bc3c31a5
Warning fixes
2016-05-14 14:01:27 +02:00
7a7c3b9b9f
More VFPU, vmmul thoughts
2016-05-14 14:00:01 +02:00
efc8a8e353
Hack to make Symbian build.
2016-05-13 23:56:17 -07:00
b7091a8f5d
Simplifications and fixes
2016-05-13 21:02:23 +02:00
5b2504120d
Optimize some common prefixes
2016-05-13 20:15:20 +02:00
91a6cf5e44
Add a couple more passes (2-op, optimize f<->v fp moves)
2016-05-13 20:14:03 +02:00
f636b2a315
Minor build and other fixes
2016-05-13 19:31:27 +02:00
9e3572dc63
jit-ir: Improve vidt to handle more cases.
2016-05-12 22:40:26 -07:00
57b3dbff7e
jit-ir: Avoid flushing on a few Vec4 ops.
2016-05-12 21:01:46 -07:00
9f183c97ba
jit-ir: Prevent reading ahead for each reg write.
2016-05-12 18:30:55 -07:00
d06c6c080c
jit-ir: Expand unused regs to regular GPRs.
2016-05-12 18:30:55 -07:00
99468c6fc1
jit-ir: Optimize out unused temp regs.
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This way, if constants have made the temp obsolete (common with ins, for
example), it won't even get set anymore.
2016-05-12 18:30:53 -07:00
850d0abc91
IR: More VFPU. Support normal fp compares.
2016-05-12 20:16:15 +02:00
2cbfb192c4
IR: Lots more VFPU support, some with SIMD
2016-05-12 12:17:25 +02:00
db1d1ff9fd
IR: Merge the FPU and VFPU instruction sets, no reason to keep them apart
2016-05-10 22:55:27 +02:00
45efcda6b1
IR: Some more VFPU
2016-05-10 21:50:08 +02:00
558bb197c7
More VFPU
2016-05-09 23:47:56 +02:00
6e44e97ffa
Refactor prep: Split JitInterface into MIPSFrontendInterface and JitInterface
2016-05-09 19:41:39 +02:00
f50617d679
Skip const flush on set float constant
2016-05-09 18:47:53 +02:00
f6d245f3c4
jit-ir: Remove redundant simplify pass.
...
This is just doing the same thing as the const folding pass, really.
2016-05-09 00:13:01 -07:00
f638477b9a
jit-ir: Add the rest to PropagateConstants.
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Just for completeness.
2016-05-08 22:17:39 -07:00
6bd31ecb27
jit-ir: Flush consts better for a few f/v ops.
2016-05-08 21:37:46 -07:00
5221a02db4
jit-ir: Propagate constants for shifts.
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This might optimize away an IRTEMP_0 in such cases.
2016-05-08 19:11:58 -07:00
a1b4b5170c
jit-ir: Propagate constants even for overlaps.
2016-05-08 19:05:39 -07:00
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