e51c58716b
Fix minor code issues flagged by PVS-Studio and reported by alphrixus.
2024-10-10 14:10:30 +02:00
e01ca5b057
Logging API change (refactor) ( #19324 )
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* Rename LogType to Log
* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.
* Mac/ARM64 buildfix
* Do the same with the hle result log macros
* Rename the log names to mixed case while at it.
* iOS buildfix
* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
5bfc0259be
Optimize away the redundant vector loads in the Wipeout games.
2024-06-08 23:22:58 +02:00
c9ca3904d3
Combine move-from-gpr and float cast.
2024-06-08 22:59:48 +02:00
0abcd00372
IR Interpreter: Don't split up lone lwr/swr/lwl/swl instructions, the interpreter handles them faster.
2024-06-08 22:28:11 +02:00
0c246297d2
Create an IR op for a FPRtoGPR + shift-right-8, very common
2024-06-07 21:26:20 +02:00
bd0beb68a4
Add new IR optimization pass, OptimizeLoadsAfterStores
2024-06-07 19:32:37 +02:00
da88011805
Specialize a few arithmetic instructions for the interpreter.
2024-06-07 19:32:37 +02:00
bdf7f5f40f
IRInterpreter: Fix issue where we could accidentally optimize out CallReplacement ops.
2024-05-26 00:12:48 +02:00
5e813e6bd6
irjit: Correct bad Vec4 overlap handling.
2023-10-14 20:54:40 -07:00
cd46f0b4cb
irjit: Cache IR metadata lookups.
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This improves compilation performance, because all those lookups were
adding up.
2023-09-30 15:56:53 -07:00
69b8fb9bc2
irjit: Correct alignment checks against SP.
2023-09-23 13:15:06 -07:00
739e474957
irjit: Improve dot and store vec4 interaction.
2023-09-01 22:35:59 -07:00
2ca638868c
irjit: Remove Vec4Scale/Vec4Dot aliasing in pass.
2023-09-01 22:35:59 -07:00
96c90c19c6
irjit: Reduce unnecessary shuffles.
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If it's never used as a Vec4 again, it's often not worth it.
2023-09-01 22:35:59 -07:00
5f84887dea
irjit: Add a pass to keep Vec4s in Vec4s.
2023-09-01 22:35:59 -07:00
ae0af175de
Merge pull request #18004 from unknownbrackets/x86-jit-minor
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x86jit: Small cleanup and tweaks, downcountInRegster, GetFPRLaneCount bugfix
2023-08-29 08:01:47 +02:00
14d871730f
x86jit: Optimize slow memory.
2023-08-28 21:16:38 -07:00
8e8605935e
irjit: Detect subtract-to-zero as constant.
2023-08-28 21:09:56 -07:00
4e90bd5070
x86jit: Use NEG more automatically for Sub x,0,y.
2023-08-28 21:09:56 -07:00
f263698897
irjit: Cleanup temp purging on exit.
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We were sometimes considering it read by exit and not purging.
2023-08-27 12:26:05 -07:00
552cd88938
irjit: Skip some work in PurgeTemps.
2023-08-20 08:59:47 -07:00
57123e8f9e
irjit: Reserve some arrays that churn.
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Improves IR compile time by around 20-30%.
2023-08-20 08:59:47 -07:00
2cdcc413b7
Merge pull request #17898 from unknownbrackets/irjit-vfputemps
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irjit: Cleanup/purge FPU/VFPU temps
2023-08-13 21:08:00 +02:00
2b36e0a625
irjit: ZeroFpCond -> FpCondFromReg.
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We already have a zero reg, so this is more useful and symmetrical.
2023-08-13 10:40:47 -07:00
fa53b80574
irjit: Cleanup/purge FPU/VFPU temps.
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A lot of cases are followed by an FMov that just moved the temp to a
regular register, from VFPU instructions playing safe about overlaps.
2023-08-13 10:14:10 -07:00
31ff23746c
irjit: Prefer ExitToConst over ExitToReg.
2023-08-08 23:14:01 -07:00
3f97545f99
irjit: Reduce exits from constants.
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This reduces bloat a bit, and may help with common funcs that enter short
loops.
2023-08-08 23:05:14 -07:00
5f9a8fd1a1
irjit: Rename IRRegCache to IRImmRegCache.
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For clarity, since it's not a native regcache.
2023-08-08 23:05:14 -07:00
e9431d0d1e
Merge pull request #17859 from unknownbrackets/irjit-vec4
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irjit: Use Vec4 a bit more
2023-08-06 23:05:33 +02:00
79ca880ac7
irjit: Implement vqmul, add Vec4Blend.
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Should be useful more places.
2023-08-06 13:38:00 -07:00
a32889d3ca
irjit: Consistently dirty vfpuctrl in IR.
2023-08-06 08:36:19 -07:00
b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit
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riscv: Spill registers more intelligently
2023-07-30 14:49:37 -07:00
f870271011
riscv: Spill registers more intelligently.
2023-07-30 14:24:12 -07:00
5db6b11ef2
irjit: Cleanup self-fmovs.
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These were sometimes getting emitted.
2023-07-30 14:16:17 -07:00
180bda6f6b
Merge pull request #17799 from unknownbrackets/irjit-lsu
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Add ll/sc to IR and x86jit
2023-07-30 09:15:55 +02:00
e228748449
irjit: Add FCvtScaledSW to safely scale vi2f.
2023-07-29 18:30:15 -07:00
a5a2671af3
irjit: Implement vf2ix.
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Used in LittleBigPlanet when playing intro movies.
2023-07-29 18:01:08 -07:00
df2462b1d9
irjit: Implement ll/sc.
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These occur more than I expected in LittleBigPlanet while loading.
2023-07-29 17:57:44 -07:00
48586ed0ad
irjit: Combine Load32Left/Right even on unaligned.
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This helps on devices that don't allow unaligned load/store.
2023-07-29 17:57:25 -07:00
df313bd296
riscv: Fix rounding mode setting.
2023-07-25 20:33:56 -07:00
9157d992ac
jit-ir: Implement cfc1/ctc1.
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This makes it so we can track rounding mode changes.
2023-07-25 20:33:56 -07:00
90517ace59
irjit: Validate alignment in slow memory mode.
2022-08-21 13:24:10 -07:00
6715f41410
irjit: Add constructs for validing mem access.
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Basically to allow slow/fast memory to work with IR, including for
alignment checks.
2022-08-21 13:01:23 -07:00
7b081a61c8
irjit: Correct another PurgeTemps case.
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In this case:
Mov A, B
AndConst A, A, 1
Load32 C, A, 0
Was still swapping the Load32 to B, not just the AndConst.
Fixes #15735 .
2022-07-27 19:38:16 -07:00
5abf1362a2
irjit: Clarify PurgeTemps, guard a couple ops.
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Although I think we skip simplify passes on breakpoints entirely, safer to
exclude these ops.
2022-07-27 19:36:53 -07:00
2154f747fc
irjit: Simplify more arithmetic to Movs.
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Later passes rely on things being Mov, so better to have them more often.
2022-07-24 11:35:54 -07:00
8f23025209
irjit: Add tests for IR passes.
2022-07-24 11:35:54 -07:00
c2a1caa2a2
irjit: Prevent corruption on purge temps pass.
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If a switch occurs and then something clobbers the dest of that switch, we
were wiping out the first of those three instructions incorrectly.
2022-07-21 09:06:37 -07:00
f32f89dd90
Global: Remove some unused variables.
2021-02-15 11:59:45 -08:00
Henrik Rydgård