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365 Commits
Author SHA1 Message Date
Unknown W. Brackets 14e2e1ed62 x64jit: Optimize FCmpVfpuAggregate. 2023-09-23 14:31:46 -07:00
Henrik Rydgård e64d1e94fe add reporting to the invalid replacement op 2023-09-23 11:39:20 +02:00
Henrik Rydgård 8fc01e37d9 Check for bad indices in GetReplacementFunc to avoid crashes 2023-09-23 10:09:55 +02:00
Henrik Rydgård 8a90e94e74 Add an assert to try to track down a mysterious reported crash. 2023-09-21 12:08:16 +02:00
Unknown W. Brackets 7a5cdafdf3 arm64jit: Implement convert/int conversions. 2023-09-08 00:03:12 -07:00
Unknown W. Brackets b698c673a8 arm64jit: Implement FSat. 2023-09-08 00:03:12 -07:00
Unknown W. Brackets c523273d51 arm64jit: Implement vector unpacks. 2023-09-08 00:03:12 -07:00
Unknown W. Brackets e03ae26d20 arm64jit: Implement vuc2i. 2023-09-08 00:02:53 -07:00
Unknown W. Brackets a21a882add arm64jit: Implement a few vector ops. 2023-09-08 00:02:53 -07:00
Unknown W. Brackets a8f81b4289 arm64jit: Add breakpoints/memchecks. 2023-09-08 00:02:53 -07:00
Henrik RydgårdandGitHub 0a234df037 Merge pull request #18089 from unknownbrackets/arm64jit-float 
arm64jit: Implement VFPU compare, trig, couple others
 2023-09-08 08:33:22 +02:00
Unknown W. Brackets 5617d08620 arm64jit: Remove unused variable. 2023-09-07 17:26:30 -07:00
Nemoumbra 0faa1109d2 Included <algorithm> for std::min 2023-09-07 12:14:36 +03:00
Unknown W. Brackets 03f22beefd arm64jit: Implement Vec2Pack32To16. 2023-09-06 20:20:52 -07:00
Unknown W. Brackets 178bb8416b arm64jit: Implement FSpecial. 2023-09-06 20:08:36 -07:00
Unknown W. Brackets fad24e3b44 arm64jit: Implement FSign. 2023-09-06 19:53:49 -07:00
Unknown W. Brackets a1304f6ac8 arm64jit: Implement VFPU compare in IR. 2023-09-06 19:02:24 -07:00
Unknown W. Brackets 01ed48a3d0 arm64jit: Implement FCvtSW. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets 89a9584c38 arm64jit: Implement FRound/similar. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets 97d9a7f07f arm64jit: Implement FCmp. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets c8f888fab0 arm64jit: Implement FMin/FMax. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets 953d97b54a arm64jit: Implement Vec4Init. 2023-09-05 00:10:26 -07:00
Unknown W. Brackets 11f92b4684 arm64jit: Implement Vec4Dot. 2023-09-05 00:10:26 -07:00
Unknown W. Brackets 81aeb04788 arm64jit: Implement Vec4Blend. 2023-09-05 00:10:26 -07:00
Unknown W. Brackets 85387b44a1 arm64jit: Implement Vec4Scale. 2023-09-05 00:10:26 -07:00
Unknown W. BracketsandGitHub 3f29b4c713 Merge pull request #18068 from unknownbrackets/arm64jit-shuffle 
arm64jit: Implement shuffle optimizer
 2023-09-05 00:10:08 -07:00
Unknown W. Brackets d8231ecb17 arm64jit: Implement divide in IR. 2023-09-04 23:38:55 -07:00
Unknown W. Brackets c272284043 arm64jit: Implement multiplies in IR. 2023-09-04 23:38:55 -07:00
Unknown W. Brackets 17ffc9c261 arm64jit: Special case some shuffles. 
To avoid 4 instruction shuffles.
 2023-09-04 23:37:40 -07:00
Unknown W. Brackets 885ae5c805 arm64jit: Implement shuffle optimizer. 2023-09-04 12:27:39 -07:00
Henrik RydgårdandGitHub 9690a71a14 Merge pull request #18061 from unknownbrackets/arm64-ir-jit 
arm64jit: Implement most ALU and load/store in IR jit
 2023-09-04 10:02:24 +02:00
Unknown W. BracketsandGitHub 494aab62fc Merge pull request #18063 from unknownbrackets/arm64-ir-float 
arm64jit: Add some initial float and vec4 ops
 2023-09-04 00:08:08 -07:00
Unknown W. Brackets 85b80bc9e5 arm64jit: Implement load/store in IR. 2023-09-04 00:04:36 -07:00
Unknown W. Brackets ccee8e41ee arm64jit: Implement exits. 2023-09-03 21:16:08 -07:00
Unknown W. Brackets e02426cbbf arm64jit: Implement some system ops. 2023-09-03 21:16:08 -07:00
Unknown W. Brackets 0933381b9e arm64jit: Add some simple vec4 ops. 2023-09-03 21:14:58 -07:00
Unknown W. Brackets 87b9633258 arm64jit: Add some simple float ops. 2023-09-03 21:14:58 -07:00
Unknown W. Brackets c44f0e1fca arm64jit: Implement most ALU in IR jit. 2023-09-03 15:30:55 -07:00
Unknown W. Brackets 7607280837 arm64jit: Implement just the most basic ops. 
This improves the slowness a good bit.
 2023-09-03 12:20:16 -07:00
Unknown W. Brackets 1b756ff8c1 arm64jit: Add initial base for IR jit. 
This works, but very slowly at this point.
 2023-09-03 12:14:28 -07:00
Henrik Rydgård c59e9e51b2 Non-change to see if CI fixes itself.. 2023-08-25 12:39:19 +02:00
Unknown W. Brackets 74e5e43fdc jit: Skip known prefix writes. 
If we already know what's in memory and it's default, we can skip
overwriting with default values.  This is common, actually.
 2023-08-22 23:26:31 -07:00
Unknown W. Brackets df2462b1d9 irjit: Implement ll/sc. 
These occur more than I expected in LittleBigPlanet while loading.
 2023-07-29 17:57:44 -07:00
Henrik RydgårdandGitHub 4aa2b1fcac Merge pull request #17783 from unknownbrackets/riscv-jit 
Implement float/vec operations in RISC-V jit
 2023-07-28 08:38:19 +02:00
Unknown W. Brackets 067a033dc0 riscv: Add FPU regcache. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets c3db3d5187 arm64jit: When rouding unset, use nearest. 
The 0/default rounding mode is nearest, not toward zero.
We set hasSetRounding only when fcr31 has a non-zero rounding mode or
flush to zero set.
 2023-07-25 20:30:05 -07:00
Unknown W. Brackets 8ee73264bf riscv: Correct depointerify on FlushAll(). 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 47b81985bd riscv: Initial untested dispatcher. 
The minimum to actually, probably, running code.  Pretty slow.
 2023-07-23 18:01:00 -07:00
Henrik Rydgård 4a4cd3d977 Add logging when loading a save state that has "unknown-prefix-mode" set 2023-06-14 10:23:23 +02:00
Henrik RydgårdandGitHub 67a35d3476 Merge pull request #17356 from unknownbrackets/minor-cleanup 
Cleanup some more string formats, mostly in debugger
 2023-05-23 08:29:23 +02:00