preserve-emulation/ppsspp
1
0 Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2026-10-19 09:19:05 +02:00
Code Issues Packages Projects Releases Wiki Activity

x86 Jit: Generate nicer code for some cases of addiu

Browse Source
This commit is contained in:
Henrik Rydgård committed 2014-10-12 17:47:53 +02:00
1 parent 25a26eeaf9
commit f99c2cd010
3 files changed
+21 -9
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Common/x64Emitter.h
+7
View File
@@ -216,6 +216,13 @@ inline OpArg Imm8 (u8 imm) {return OpArg(imm, SCALE_IMM8);}
inline OpArg Imm16(u16 imm) {return OpArg(imm, SCALE_IMM16);} //rarely used
inline OpArg Imm32(u32 imm) {return OpArg(imm, SCALE_IMM32);}
inline OpArg Imm64(u64 imm) {return OpArg(imm, SCALE_IMM64);}
inline OpArg UImmAuto(u32 imm) {
return OpArg(imm, imm >= 128 ? SCALE_IMM32 : SCALE_IMM8);
}
inline OpArg SImmAuto(s32 imm) {
return OpArg(imm, (imm >= 128 || imm < -128) ? SCALE_IMM32 : SCALE_IMM8);
}
#ifdef _M_X64
inline OpArg ImmPtr(const void *imm) {return Imm64((u64)imm);}
#else
Core/MIPS/x86/Asm.cpp
-1
View File
@@ -115,7 +115,6 @@ void AsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
AND(32, R(EDX), Imm32(MIPS_JITBLOCK_MASK));
CMP(32, R(EDX), Imm32(MIPS_EMUHACK_OPCODE));
FixupBranch notfound = J_CC(CC_NZ);
// IDEA - we have 24 bits, why not just use offsets from base of code?
if (enableDebug)
{
ADD(32, M(&mips->debugCount), Imm8(1));
Core/MIPS/x86/CompALU.cpp
+14 -8
View File
@@ -75,28 +75,34 @@ namespace MIPSComp
case 8: // same as addiu?
case 9: // R(rt) = R(rs) + simm; break; //addiu
{
if (gpr.IsImm(rs))
{
if (gpr.IsImm(rs)) {
gpr.SetImm(rt, gpr.GetImm(rs) + simm);
break;
}
gpr.Lock(rt, rs);
gpr.MapReg(rt, rt == rs, true);
if (rt == rs || gpr.R(rs).IsSimpleReg())
if (rt == rs) {
if (simm > 0) {
ADD(32, gpr.R(rt), UImmAuto(simm));
} else if (simm < 0) {
SUB(32, gpr.R(rt), UImmAuto(-simm));
}
} else if (gpr.R(rs).IsSimpleReg()) {
LEA(32, gpr.RX(rt), MDisp(gpr.RX(rs), simm));
else
{
} else {
MOV(32, gpr.R(rt), gpr.R(rs));
if (suimm != 0)
ADD(32, gpr.R(rt), Imm32(suimm));
if (simm > 0)
ADD(32, gpr.R(rt), UImmAuto(simm));
else if (simm < 0) {
SUB(32, gpr.R(rt), UImmAuto(-simm));
}
}
gpr.UnlockAll();
}
break;
case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
// There's a mips compiler out there asking questions it already knows the answer to...
if (gpr.IsImm(rs))
{
gpr.SetImm(rt, (s32)gpr.GetImm(rs) < simm);