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ARM emitter: Complete VLD1/VST1 for lanes and to-all-lanes.
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Henrik Rydgard committed
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cda4e9cbf3
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-48
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+68
-23
@@ -1177,6 +1177,21 @@ u32 EncodeVm(ARMReg Vm)
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}
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}
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u32 encodedSize(u32 value)
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{
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if (value & I_8)
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return 0;
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else if (value & I_16)
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return 1;
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else if ((value & I_32) || (value & F_32))
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return 2;
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else if (value & I_64)
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return 3;
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else
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_dbg_assert_msg_(JIT, false, "Passed invalid size to integer NEON instruction");
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return 0;
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}
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ARMReg SubBase(ARMReg Reg)
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{
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if (Reg >= S0)
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@@ -2369,43 +2384,72 @@ static int RegCountToType(int nRegs, NEONAlignment align) {
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}
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}
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void ARMXEmitter::VLD1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align, ARMReg Rm)
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void ARMXEmitter::VLDST1(bool load, u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align, ARMReg Rm)
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{
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u32 spacing = RegCountToType(regCount, align); // Only support loading to 1 reg
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// Gets encoded as a double register
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Vd = SubBase(Vd);
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Write32((0xF4 << 24) | ((Vd & 0x10) << 18) | (1 << 21) | (Rn << 16)
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Write32((0xF4 << 24) | ((Vd & 0x10) << 18) | (load << 21) | (Rn << 16)
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| ((Vd & 0xF) << 12) | (spacing << 8) | (encodedSize(Size) << 6)
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| (align << 4) | Rm);
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}
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void ARMXEmitter::VST1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align, ARMReg Rm)
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void ARMXEmitter::VLD1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align, ARMReg Rm) {
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VLDST1(true, Size, Vd, Rn, regCount, align, Rm);
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}
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void ARMXEmitter::VST1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align, ARMReg Rm) {
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VLDST1(false, Size, Vd, Rn, regCount, align, Rm);
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}
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void ARMXEmitter::VLDST1_lane(bool load, u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm)
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{
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u32 spacing = RegCountToType(regCount, align); // Only support loading to 1 reg
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// Gets encoded as a double register
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bool register_quad = Vd >= Q0;
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Vd = SubBase(Vd);
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// Support quad lanes by converting to D lanes
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if (register_quad && lane > 1) {
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Vd = (ARMReg)((int)Vd + 1);
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lane -= 2;
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}
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int encSize = encodedSize(Size);
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int index_align = 0;
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switch (encSize) {
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case 0: index_align = lane << 1; break;
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case 1: index_align = lane << 2; if (aligned) index_align |= 1; break;
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case 2: index_align = lane << 3; if (aligned) index_align |= 3; break;
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default:
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break;
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}
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Write32((0xF4 << 24) | (1 << 23) | ((Vd & 0x10) << 18) | (load << 21) | (Rn << 16)
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| ((Vd & 0xF) << 12) | (encSize << 10)
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| (index_align << 4) | Rm);
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}
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void ARMXEmitter::VLD1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm) {
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VLDST1_lane(true, Size, Vd, Rn, lane, aligned, Rm);
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}
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void ARMXEmitter::VST1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm) {
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VLDST1_lane(false, Size, Vd, Rn, lane, aligned, Rm);
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}
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void ARMXEmitter::VLD1_all_lanes(u32 Size, ARMReg Vd, ARMReg Rn, bool aligned, ARMReg Rm) {
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bool register_quad = Vd >= Q0;
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Vd = SubBase(Vd);
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Write32((0xF4 << 24) | ((Vd & 0x10) << 18) | (Rn << 16)
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| ((Vd & 0xF) << 12) | (spacing << 8) | (encodedSize(Size) << 6)
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| (align << 4) | Rm);
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int T = register_quad; // two D registers
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Write32((0xF4 << 24) | (1 << 23) | ((Vd & 0x10) << 18) | (1 << 21) | (Rn << 16)
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| ((Vd & 0xF) << 12) | (0xC << 8) | (encodedSize(Size) << 6)
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| (T << 5) | (aligned << 4) | Rm);
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}
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void ARMXEmitter::VLD1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm) {
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_dbg_assert_msg_(JIT, false, "VLD1_lane not done yet");
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// TODO
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}
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void ARMXEmitter::VST1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm) {
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_dbg_assert_msg_(JIT, false, "VST1_lane not done yet");
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// TODO
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}
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void ARMXEmitter::VLD2(u32 Size, ARMReg Vd, ARMReg Rn, NEONAlignment align, ARMReg Rm)
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/*
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void ARMXEmitter::VLD2(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align, ARMReg Rm)
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{
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u32 spacing = 0x8; // Single spaced registers
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// Gets encoded as a double register
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@@ -2415,6 +2459,7 @@ void ARMXEmitter::VLD2(u32 Size, ARMReg Vd, ARMReg Rn, NEONAlignment align, ARMR
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| ((Vd & 0xF) << 12) | (spacing << 8) | (encodedSize(Size) << 6)
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| (align << 4) | Rm);
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}
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*/
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void ARMXEmitter::VREVX(u32 size, u32 Size, ARMReg Vd, ARMReg Vm)
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{
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+32
-25
@@ -70,6 +70,9 @@ enum ARMReg
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// ASIMD Quad-Word registers
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Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
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Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15,
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// for NEON VLD/VST instructions
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REG_UPDATE = R13,
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INVALID_REG = 0xFFFFFFFF
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};
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@@ -360,6 +363,8 @@ u32 EncodeVd(ARMReg Vd);
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u32 EncodeVn(ARMReg Vn);
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u32 EncodeVm(ARMReg Vm);
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u32 encodedSize(u32 value);
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// Subtracts the base from the register to give us the real one
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ARMReg SubBase(ARMReg Reg);
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@@ -720,26 +725,44 @@ public:
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// Notes:
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// Rm == _PC is interpreted as no offset, otherwise, effective address is sum of Rn and Rm
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// Rm == R13 is interpreted as VLD1, .... [Rn]!
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// Rm == R13 is interpreted as VLD1, .... [Rn]! Added a REG_UPDATE pseudo register.
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// Load/store multiple registers full of elements (a register is a D register)
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// Specifying alignment when it can be guaranteed is documented to improve load/store performance.
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// For example, when loading a set of four 64-bit registers that we know is 32-byte aligned, we should specify ALIGN_256.
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void VLDST1(bool load, u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align, ARMReg Rm);
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void VLD1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
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void VST1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
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// Load/store single lanes of D registers
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// TODO
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void VLD1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
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void VST1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
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// TODO: Make quad-oriented wrappers for the above.
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void VLDST1_lane(bool load, u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm);
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void VLD1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm = _PC);
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void VST1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm = _PC);
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// Load one value into all lanes of a D or a Q register (either supported, all formats should work).
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void VLD1_all_lanes(u32 Size, ARMReg Vd, ARMReg Rn, bool aligned, ARMReg Rm = _PC);
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/*
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// Deinterleave two loads... or something. TODO
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void VLD2(u32 Size, ARMReg Vd, ARMReg Rn, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
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void VLD2(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
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void VST2(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
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void VLD2_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
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void VST2_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
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void VLD3(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
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void VST3(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
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void VLD3_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
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void VST3_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
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void VLD4(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
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void VST4(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
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void VLD4_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
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void VST4_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
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*/
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void VMRS_APSR();
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void VMRS(ARMReg Rt);
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@@ -761,22 +784,6 @@ public:
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void CMPI2R(ARMReg rs, u32 val, ARMReg scratch);
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void TSTI2R(ARMReg rs, u32 val, ARMReg scratch);
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void ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
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inline u32 encodedSize(u32 value)
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{
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if (value & I_8)
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return 0;
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else if (value & I_16)
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return 1;
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else if ((value & I_32) || (value & F_32))
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return 2;
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else if (value & I_64)
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return 3;
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else
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_dbg_assert_msg_(JIT, false, "Passed invalid size to integer NEON instruction");
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return 0;
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}
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}; // class ARMXEmitter
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