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armjit: Improve GPR typesafety.

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Unknown W. Brackets committed 2013-11-09 08:24:15 -08:00
1 parent 945b8bf5c5
commit cb3bb73148
7 files changed
+120 -118
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Core/MIPS/ARM/ArmCompLoadStore.cpp
+2 -2
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@@ -66,7 +66,7 @@
namespace MIPSComp
{
void Jit::SetR0ToEffectiveAddress(int rs, s16 offset) {
void Jit::SetR0ToEffectiveAddress(MIPSGPReg rs, s16 offset) {
Operand2 op2;
if (offset) {
bool negated;
@@ -91,7 +91,7 @@ namespace MIPSComp
}
}
void Jit::SetCCAndR0ForSafeAddress(int rs, s16 offset, ARMReg tempReg) {
void Jit::SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg) {
SetR0ToEffectiveAddress(rs, offset);
// There are three valid ranges. Each one gets a bit.