diff --git a/Core/MIPS/ARM/ArmCompALU.cpp b/Core/MIPS/ARM/ArmCompALU.cpp index 3499037d70..7bf8fb8265 100644 --- a/Core/MIPS/ARM/ArmCompALU.cpp +++ b/Core/MIPS/ARM/ArmCompALU.cpp @@ -50,7 +50,7 @@ namespace MIPSComp static u32 EvalAdd(u32 a, u32 b) { return a + b; } static u32 EvalSub(u32 a, u32 b) { return a - b; } - void Jit::CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b)) + void Jit::CompImmLogic(MIPSGPReg rs, MIPSGPReg rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b)) { if (gpr.IsImm(rs)) { gpr.SetImm(rt, (*eval)(gpr.GetImm(rs), uimm)); @@ -145,7 +145,7 @@ namespace MIPSComp { CONDITIONAL_DISABLE; MIPSGPReg rs = _RS; - int rd = _RD; + MIPSGPReg rd = _RD; // Don't change $zr. if (rd == 0) @@ -189,7 +189,7 @@ namespace MIPSComp } } - void Jit::CompType3(int rd, int rs, int rt, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool symmetric, bool useMOV) + void Jit::CompType3(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool symmetric, bool useMOV) { if (gpr.IsImm(rs) && gpr.IsImm(rt)) { gpr.SetImm(rd, (*eval)(gpr.GetImm(rs), gpr.GetImm(rt))); @@ -197,7 +197,7 @@ namespace MIPSComp } if (gpr.IsImm(rt) || (gpr.IsImm(rs) && symmetric)) { - int lhs = gpr.IsImm(rs) ? rt : rs; + MIPSGPReg lhs = gpr.IsImm(rs) ? rt : rs; u32 rhsImm = gpr.IsImm(rs) ? gpr.GetImm(rs) : gpr.GetImm(rt); Operand2 op2; // TODO: AND could be reversed, OR/EOR could use multiple ops (maybe still cheaper.) @@ -230,7 +230,7 @@ namespace MIPSComp CONDITIONAL_DISABLE; MIPSGPReg rt = _RT; MIPSGPReg rs = _RS; - int rd = _RD; + MIPSGPReg rd = _RD; // noop, won't write to ZERO. if (rd == 0) @@ -315,8 +315,8 @@ namespace MIPSComp if (gpr.IsImm(rs) && gpr.IsImm(rt)) { gpr.SetImm(rd, ~(gpr.GetImm(rs) | gpr.GetImm(rt))); } else if (gpr.IsImm(rs) || gpr.IsImm(rt)) { - int lhs = gpr.IsImm(rs) ? rt : rs; - int rhs = gpr.IsImm(rs) ? rs : rt; + MIPSGPReg lhs = gpr.IsImm(rs) ? rt : rs; + MIPSGPReg rhs = gpr.IsImm(rs) ? rs : rt; u32 rhsImm = gpr.GetImm(rhs); Operand2 op2; if (TryMakeOperand2(rhsImm, op2)) { @@ -452,7 +452,7 @@ namespace MIPSComp void Jit::CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType) { - int rd = _RD; + MIPSGPReg rd = _RD; MIPSGPReg rt = _RT; int sa = _SA; @@ -462,7 +462,7 @@ namespace MIPSComp void Jit::CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType) { - int rd = _RD; + MIPSGPReg rd = _RD; MIPSGPReg rt = _RT; MIPSGPReg rs = _RS; if (gpr.IsImm(rs)) @@ -481,7 +481,7 @@ namespace MIPSComp { CONDITIONAL_DISABLE; MIPSGPReg rs = _RS; - int rd = _RD; + MIPSGPReg rd = _RD; int fd = _FD; // noop, won't write to ZERO. @@ -574,7 +574,7 @@ namespace MIPSComp { CONDITIONAL_DISABLE; MIPSGPReg rt = _RT; - int rd = _RD; + MIPSGPReg rd = _RD; // Don't change $zr. if (rd == 0) return; @@ -632,7 +632,7 @@ namespace MIPSComp { CONDITIONAL_DISABLE; MIPSGPReg rt = _RT; - int rd = _RD; + MIPSGPReg rd = _RD; // Don't change $zr. if (rd == 0) return; @@ -658,47 +658,47 @@ namespace MIPSComp CONDITIONAL_DISABLE; MIPSGPReg rt = _RT; MIPSGPReg rs = _RS; - int rd = _RD; + MIPSGPReg rd = _RD; switch (op & 63) { case 16: // R(rd) = HI; //mfhi - gpr.MapDirtyIn(rd, MIPSREG_HI); - MOV(gpr.R(rd), gpr.R(MIPSREG_HI)); + gpr.MapDirtyIn(rd, MIPS_REG_HI); + MOV(gpr.R(rd), gpr.R(MIPS_REG_HI)); break; case 17: // HI = R(rs); //mthi - gpr.MapDirtyIn(MIPSREG_HI, rs); - MOV(gpr.R(MIPSREG_HI), gpr.R(rs)); + gpr.MapDirtyIn(MIPS_REG_HI, rs); + MOV(gpr.R(MIPS_REG_HI), gpr.R(rs)); break; case 18: // R(rd) = LO; break; //mflo - gpr.MapDirtyIn(rd, MIPSREG_LO); - MOV(gpr.R(rd), gpr.R(MIPSREG_LO)); + gpr.MapDirtyIn(rd, MIPS_REG_LO); + MOV(gpr.R(rd), gpr.R(MIPS_REG_LO)); break; case 19: // LO = R(rs); break; //mtlo - gpr.MapDirtyIn(MIPSREG_LO, rs); - MOV(gpr.R(MIPSREG_LO), gpr.R(rs)); + gpr.MapDirtyIn(MIPS_REG_LO, rs); + MOV(gpr.R(MIPS_REG_LO), gpr.R(rs)); break; case 24: //mult (the most popular one). lo,hi = signed mul (rs * rt) - gpr.MapDirtyDirtyInIn(MIPSREG_LO, MIPSREG_HI, rs, rt); - SMULL(gpr.R(MIPSREG_LO), gpr.R(MIPSREG_HI), gpr.R(rs), gpr.R(rt)); + gpr.MapDirtyDirtyInIn(MIPS_REG_LO, MIPS_REG_HI, rs, rt); + SMULL(gpr.R(MIPS_REG_LO), gpr.R(MIPS_REG_HI), gpr.R(rs), gpr.R(rt)); break; case 25: //multu (2nd) lo,hi = unsigned mul (rs * rt) - gpr.MapDirtyDirtyInIn(MIPSREG_LO, MIPSREG_HI, rs, rt); - UMULL(gpr.R(MIPSREG_LO), gpr.R(MIPSREG_HI), gpr.R(rs), gpr.R(rt)); + gpr.MapDirtyDirtyInIn(MIPS_REG_LO, MIPS_REG_HI, rs, rt); + UMULL(gpr.R(MIPS_REG_LO), gpr.R(MIPS_REG_HI), gpr.R(rs), gpr.R(rt)); break; case 26: //div if (cpu_info.bIDIVa) { - gpr.MapDirtyDirtyInIn(MIPSREG_LO, MIPSREG_HI, rs, rt); - SDIV(gpr.R(MIPSREG_LO), gpr.R(rs), gpr.R(rt)); - MUL(R0, gpr.R(rt), gpr.R(MIPSREG_LO)); - SUB(gpr.R(MIPSREG_HI), gpr.R(rs), Operand2(R0)); + gpr.MapDirtyDirtyInIn(MIPS_REG_LO, MIPS_REG_HI, rs, rt); + SDIV(gpr.R(MIPS_REG_LO), gpr.R(rs), gpr.R(rt)); + MUL(R0, gpr.R(rt), gpr.R(MIPS_REG_LO)); + SUB(gpr.R(MIPS_REG_HI), gpr.R(rs), Operand2(R0)); } else { DISABLE; } @@ -707,33 +707,33 @@ namespace MIPSComp case 27: //divu if (cpu_info.bIDIVa) { - gpr.MapDirtyDirtyInIn(MIPSREG_LO, MIPSREG_HI, rs, rt); - UDIV(gpr.R(MIPSREG_LO), gpr.R(rs), gpr.R(rt)); - MUL(R0, gpr.R(rt), gpr.R(MIPSREG_LO)); - SUB(gpr.R(MIPSREG_HI), gpr.R(rs), Operand2(R0)); + gpr.MapDirtyDirtyInIn(MIPS_REG_LO, MIPS_REG_HI, rs, rt); + UDIV(gpr.R(MIPS_REG_LO), gpr.R(rs), gpr.R(rt)); + MUL(R0, gpr.R(rt), gpr.R(MIPS_REG_LO)); + SUB(gpr.R(MIPS_REG_HI), gpr.R(rs), Operand2(R0)); } else { DISABLE; } break; case 28: //madd - gpr.MapDirtyDirtyInIn(MIPSREG_LO, MIPSREG_HI, rs, rt, false); - SMLAL(gpr.R(MIPSREG_LO), gpr.R(MIPSREG_HI), gpr.R(rs), gpr.R(rt)); + gpr.MapDirtyDirtyInIn(MIPS_REG_LO, MIPS_REG_HI, rs, rt, false); + SMLAL(gpr.R(MIPS_REG_LO), gpr.R(MIPS_REG_HI), gpr.R(rs), gpr.R(rt)); break; case 29: //maddu - gpr.MapDirtyDirtyInIn(MIPSREG_LO, MIPSREG_HI, rs, rt, false); - UMLAL(gpr.R(MIPSREG_LO), gpr.R(MIPSREG_HI), gpr.R(rs), gpr.R(rt)); + gpr.MapDirtyDirtyInIn(MIPS_REG_LO, MIPS_REG_HI, rs, rt, false); + UMLAL(gpr.R(MIPS_REG_LO), gpr.R(MIPS_REG_HI), gpr.R(rs), gpr.R(rt)); break; case 46: // msub DISABLE; - gpr.MapDirtyDirtyInIn(MIPSREG_LO, MIPSREG_HI, rs, rt, false); + gpr.MapDirtyDirtyInIn(MIPS_REG_LO, MIPS_REG_HI, rs, rt, false); break; case 47: // msubu DISABLE; - gpr.MapDirtyDirtyInIn(MIPSREG_LO, MIPSREG_HI, rs, rt, false); + gpr.MapDirtyDirtyInIn(MIPS_REG_LO, MIPS_REG_HI, rs, rt, false); break; default: diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp index 5497af18fd..cc1ac565b8 100644 --- a/Core/MIPS/ARM/ArmCompLoadStore.cpp +++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp @@ -66,7 +66,7 @@ namespace MIPSComp { - void Jit::SetR0ToEffectiveAddress(int rs, s16 offset) { + void Jit::SetR0ToEffectiveAddress(MIPSGPReg rs, s16 offset) { Operand2 op2; if (offset) { bool negated; @@ -91,7 +91,7 @@ namespace MIPSComp } } - void Jit::SetCCAndR0ForSafeAddress(int rs, s16 offset, ARMReg tempReg) { + void Jit::SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg) { SetR0ToEffectiveAddress(rs, offset); // There are three valid ranges. Each one gets a bit. diff --git a/Core/MIPS/ARM/ArmJit.h b/Core/MIPS/ARM/ArmJit.h index ddbe48169c..dc2ae881cc 100644 --- a/Core/MIPS/ARM/ArmJit.h +++ b/Core/MIPS/ARM/ArmJit.h @@ -160,8 +160,8 @@ private: void BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely); // Utilities to reduce duplicated code - void CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b)); - void CompType3(int rd, int rs, int rt, void (ARMXEmitter::*arithOp2)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool symmetric = false, bool useMOV = false); + void CompImmLogic(MIPSGPReg rs, MIPSGPReg rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b)); + void CompType3(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, void (ARMXEmitter::*arithOp2)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool symmetric = false, bool useMOV = false); void CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType); void CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType); @@ -181,8 +181,8 @@ private: void GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg); // Utils - void SetR0ToEffectiveAddress(int rs, s16 offset); - void SetCCAndR0ForSafeAddress(int rs, s16 offset, ARMReg tempReg); + void SetR0ToEffectiveAddress(MIPSGPReg rs, s16 offset); + void SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg); JitBlockCache blocks; ArmJitOptions jo; diff --git a/Core/MIPS/ARM/ArmRegCache.cpp b/Core/MIPS/ARM/ArmRegCache.cpp index 322eeb8b73..73e909d593 100644 --- a/Core/MIPS/ARM/ArmRegCache.cpp +++ b/Core/MIPS/ARM/ArmRegCache.cpp @@ -34,7 +34,7 @@ void ArmRegCache::Init(ARMXEmitter *emitter) { void ArmRegCache::Start(MIPSAnalyst::AnalysisResults &stats) { for (int i = 0; i < NUM_ARMREG; i++) { - ar[i].mipsReg = -1; + ar[i].mipsReg = MIPS_REG_INVALID; ar[i].isDirty = false; } for (int i = 0; i < NUM_MIPSREG; i++) { @@ -74,7 +74,7 @@ void ArmRegCache::FlushBeforeCall() { FlushArmReg(R12); } -ARMReg ArmRegCache::MapRegAsPointer(MIPSReg mipsReg) { // read-only, non-dirty. +ARMReg ArmRegCache::MapRegAsPointer(MIPSGPReg mipsReg) { // read-only, non-dirty. // If already mapped as a pointer, bail. if (mr[mipsReg].loc == ML_ARMREG_AS_PTR) { return mr[mipsReg].reg; @@ -96,13 +96,13 @@ ARMReg ArmRegCache::MapRegAsPointer(MIPSReg mipsReg) { // read-only, non-dirty. return armReg; } -bool ArmRegCache::IsMappedAsPointer(MIPSReg mipsReg) { +bool ArmRegCache::IsMappedAsPointer(MIPSGPReg mipsReg) { return mr[mipsReg].loc == ML_ARMREG_AS_PTR; } // TODO: Somewhat smarter spilling - currently simply spills the first available, should do // round robin or FIFO or something. -ARMReg ArmRegCache::MapReg(MIPSReg mipsReg, int mapFlags) { +ARMReg ArmRegCache::MapReg(MIPSGPReg mipsReg, int mapFlags) { // Let's see if it's already mapped. If so we just need to update the dirty flag. // We don't need to check for ML_NOINIT because we assume that anyone who maps // with that flag immediately writes a "known" value to the register. @@ -135,47 +135,47 @@ ARMReg ArmRegCache::MapReg(MIPSReg mipsReg, int mapFlags) { allocate: for (int i = 0; i < allocCount; i++) { - int reg = allocOrder[i]; + ARMReg reg = allocOrder[i]; - if (ar[reg].mipsReg == -1) { + if (ar[reg].mipsReg == MIPS_REG_INVALID) { // That means it's free. Grab it, and load the value into it (if requested). ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false; if (!(mapFlags & MAP_NOINIT)) { if (mipsReg == 0) { // If we get a request to load the zero register, at least we won't spend // time on a memory access... - emit_->MOV((ARMReg)reg, 0); + emit_->MOV(reg, 0); } else { if (mr[mipsReg].loc == ML_MEM) { - emit_->LDR((ARMReg)reg, CTXREG, GetMipsRegOffset(mipsReg)); + emit_->LDR(reg, CTXREG, GetMipsRegOffset(mipsReg)); } else if (mr[mipsReg].loc == ML_IMM) { - emit_->MOVI2R((ARMReg)reg, mr[mipsReg].imm); + emit_->MOVI2R(reg, mr[mipsReg].imm); ar[reg].isDirty = true; // IMM is always dirty. } } } ar[reg].mipsReg = mipsReg; mr[mipsReg].loc = ML_ARMREG; - mr[mipsReg].reg = (ARMReg)reg; - return (ARMReg)reg; + mr[mipsReg].reg = reg; + return reg; } } // Still nothing. Let's spill a reg and goto 10. // TODO: Use age or something to choose which register to spill? // TODO: Spill dirty regs first? or opposite? - int bestToSpill = -1; + ARMReg bestToSpill = INVALID_REG; for (int i = 0; i < allocCount; i++) { - int reg = allocOrder[i]; - if (ar[reg].mipsReg != -1 && mr[ar[reg].mipsReg].spillLock) + ARMReg reg = allocOrder[i]; + if (ar[reg].mipsReg != MIPS_REG_INVALID && mr[ar[reg].mipsReg].spillLock) continue; bestToSpill = reg; break; } - if (bestToSpill != -1) { + if (bestToSpill != INVALID_REG) { // ERROR_LOG(JIT, "Out of registers at PC %08x - spills register %i.", mips_->pc, bestToSpill); - FlushArmReg((ARMReg)bestToSpill); + FlushArmReg(bestToSpill); goto allocate; } @@ -184,14 +184,14 @@ allocate: return INVALID_REG; } -void ArmRegCache::MapInIn(MIPSReg rd, MIPSReg rs) { +void ArmRegCache::MapInIn(MIPSGPReg rd, MIPSGPReg rs) { SpillLock(rd, rs); MapReg(rd); MapReg(rs); ReleaseSpillLocks(); } -void ArmRegCache::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) { +void ArmRegCache::MapDirtyIn(MIPSGPReg rd, MIPSGPReg rs, bool avoidLoad) { SpillLock(rd, rs); bool load = !avoidLoad || rd == rs; MapReg(rd, MAP_DIRTY | (load ? 0 : MAP_NOINIT)); @@ -199,7 +199,7 @@ void ArmRegCache::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) { ReleaseSpillLocks(); } -void ArmRegCache::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad) { +void ArmRegCache::MapDirtyInIn(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) { SpillLock(rd, rs, rt); bool load = !avoidLoad || (rd == rs || rd == rt); MapReg(rd, MAP_DIRTY | (load ? 0 : MAP_NOINIT)); @@ -208,7 +208,7 @@ void ArmRegCache::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoa ReleaseSpillLocks(); } -void ArmRegCache::MapDirtyDirtyInIn(MIPSReg rd1, MIPSReg rd2, MIPSReg rs, MIPSReg rt, bool avoidLoad) { +void ArmRegCache::MapDirtyDirtyInIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) { SpillLock(rd1, rd2, rs, rt); bool load1 = !avoidLoad || (rd1 == rs || rd1 == rt); bool load2 = !avoidLoad || (rd2 == rs || rd2 == rt); @@ -220,11 +220,11 @@ void ArmRegCache::MapDirtyDirtyInIn(MIPSReg rd1, MIPSReg rd2, MIPSReg rs, MIPSRe } void ArmRegCache::FlushArmReg(ARMReg r) { - if (ar[r].mipsReg == -1) { + if (ar[r].mipsReg == MIPS_REG_INVALID) { // Nothing to do, reg not mapped. return; } - if (ar[r].mipsReg != -1) { + if (ar[r].mipsReg != MIPS_REG_INVALID) { if (ar[r].isDirty && mr[ar[r].mipsReg].loc == ML_ARMREG) emit_->STR(r, CTXREG, GetMipsRegOffset(ar[r].mipsReg)); // IMMs won't be in an ARM reg. @@ -235,25 +235,25 @@ void ArmRegCache::FlushArmReg(ARMReg r) { ERROR_LOG(JIT, "Dirty but no mipsreg?"); } ar[r].isDirty = false; - ar[r].mipsReg = -1; + ar[r].mipsReg = MIPS_REG_INVALID; } -void ArmRegCache::DiscardR(MIPSReg mipsReg) { +void ArmRegCache::DiscardR(MIPSGPReg mipsReg) { if (mr[mipsReg].loc == ML_ARMREG || mr[mipsReg].loc == ML_ARMREG_AS_PTR) { ARMReg armReg = mr[mipsReg].reg; ar[armReg].isDirty = false; - ar[armReg].mipsReg = -1; + ar[armReg].mipsReg = MIPS_REG_INVALID; mr[mipsReg].reg = INVALID_REG; mr[mipsReg].loc = ML_MEM; mr[mipsReg].imm = 0; } } -void ArmRegCache::FlushR(MIPSReg r) { +void ArmRegCache::FlushR(MIPSGPReg r) { switch (mr[r].loc) { case ML_IMM: // IMM is always "dirty". - if (r != 0) { + if (r != MIPS_REG_ZERO) { emit_->MOVI2R(R0, mr[r].imm); emit_->STR(R0, CTXREG, GetMipsRegOffset(r)); } @@ -264,12 +264,12 @@ void ArmRegCache::FlushR(MIPSReg r) { ERROR_LOG(JIT, "FlushMipsReg: MipsReg had bad ArmReg"); } if (ar[mr[r].reg].isDirty) { - if (r != 0) { + if (r != MIPS_REG_ZERO) { emit_->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r)); } ar[mr[r].reg].isDirty = false; } - ar[mr[r].reg].mipsReg = -1; + ar[mr[r].reg].mipsReg = MIPS_REG_INVALID; break; case ML_ARMREG_AS_PTR: @@ -277,7 +277,7 @@ void ArmRegCache::FlushR(MIPSReg r) { if (ar[mr[r].reg].isDirty) { ERROR_LOG(JIT, "ARMREG_AS_PTR cannot be dirty (yet)"); } - ar[mr[r].reg].mipsReg = -1; + ar[mr[r].reg].mipsReg = MIPS_REG_INVALID; break; case ML_MEM: @@ -295,23 +295,23 @@ void ArmRegCache::FlushR(MIPSReg r) { void ArmRegCache::FlushAll() { for (int i = 0; i < NUM_MIPSREG; i++) { - FlushR(i); + FlushR(MIPSGPReg(i)); } // Sanity check for (int i = 0; i < NUM_ARMREG; i++) { - if (ar[i].mipsReg != -1) { + if (ar[i].mipsReg != MIPS_REG_INVALID) { ERROR_LOG(JIT, "Flush fail: ar[%i].mipsReg=%i", i, ar[i].mipsReg); } } } -void ArmRegCache::SetImm(MIPSReg r, u32 immVal) { - if (r == 0) +void ArmRegCache::SetImm(MIPSGPReg r, u32 immVal) { + if (r == MIPS_REG_ZERO) ERROR_LOG(JIT, "Trying to set immediate %08x to r0", immVal); // Zap existing value if cached in a reg if (mr[r].loc == ML_ARMREG || mr[r].loc == ML_ARMREG_AS_PTR) { - ar[mr[r].reg].mipsReg = -1; + ar[mr[r].reg].mipsReg = MIPS_REG_INVALID; ar[mr[r].reg].isDirty = false; } mr[r].loc = ML_IMM; @@ -319,37 +319,38 @@ void ArmRegCache::SetImm(MIPSReg r, u32 immVal) { mr[r].reg = INVALID_REG; } -bool ArmRegCache::IsImm(MIPSReg r) const { - if (r == 0) return true; +bool ArmRegCache::IsImm(MIPSGPReg r) const { + if (r == MIPS_REG_ZERO) return true; return mr[r].loc == ML_IMM; } -u32 ArmRegCache::GetImm(MIPSReg r) const { - if (r == 0) return 0; +u32 ArmRegCache::GetImm(MIPSGPReg r) const { + if (r == MIPS_REG_ZERO) return 0; if (mr[r].loc != ML_IMM) { ERROR_LOG(JIT, "Trying to get imm from non-imm register %i", r); } return mr[r].imm; } -int ArmRegCache::GetMipsRegOffset(MIPSReg r) { +int ArmRegCache::GetMipsRegOffset(MIPSGPReg r) { if (r < 32) return r * 4; switch (r) { - case MIPSREG_HI: + case MIPS_REG_HI: return offsetof(MIPSState, hi); - case MIPSREG_LO: + case MIPS_REG_LO: return offsetof(MIPSState, lo); + default: + ERROR_LOG(JIT, "bad mips register %i", r); + return 0; // or what? } - ERROR_LOG(JIT, "bad mips register %i", r); - return 0; // or what? } -void ArmRegCache::SpillLock(MIPSReg r1, MIPSReg r2, MIPSReg r3, MIPSReg r4) { +void ArmRegCache::SpillLock(MIPSGPReg r1, MIPSGPReg r2, MIPSGPReg r3, MIPSGPReg r4) { mr[r1].spillLock = true; - if (r2 != -1) mr[r2].spillLock = true; - if (r3 != -1) mr[r3].spillLock = true; - if (r4 != -1) mr[r4].spillLock = true; + if (r2 != MIPS_REG_INVALID) mr[r2].spillLock = true; + if (r3 != MIPS_REG_INVALID) mr[r3].spillLock = true; + if (r4 != MIPS_REG_INVALID) mr[r4].spillLock = true; } void ArmRegCache::ReleaseSpillLocks() { @@ -358,11 +359,11 @@ void ArmRegCache::ReleaseSpillLocks() { } } -void ArmRegCache::ReleaseSpillLock(MIPSReg reg) { +void ArmRegCache::ReleaseSpillLock(MIPSGPReg reg) { mr[reg].spillLock = false; } -ARMReg ArmRegCache::R(int mipsReg) { +ARMReg ArmRegCache::R(MIPSGPReg mipsReg) { if (mr[mipsReg].loc == ML_ARMREG) { return (ARMReg)mr[mipsReg].reg; } else { @@ -371,7 +372,7 @@ ARMReg ArmRegCache::R(int mipsReg) { } } -ARMReg ArmRegCache::RPtr(int mipsReg) { +ARMReg ArmRegCache::RPtr(MIPSGPReg mipsReg) { if (mr[mipsReg].loc == ML_ARMREG_AS_PTR) { return (ARMReg)mr[mipsReg].reg; } else { diff --git a/Core/MIPS/ARM/ArmRegCache.h b/Core/MIPS/ARM/ArmRegCache.h index b4f5209e10..3299965a5f 100644 --- a/Core/MIPS/ARM/ArmRegCache.h +++ b/Core/MIPS/ARM/ArmRegCache.h @@ -30,17 +30,14 @@ using namespace ArmGen; // R10 = MIPS context // R11 = base pointer -// Special MIPS registers: enum { - MIPSREG_HI = 32, - MIPSREG_LO = 33, TOTAL_MAPPABLE_MIPSREGS = 34, }; typedef int MIPSReg; struct RegARM { - int mipsReg; // if -1, no mipsreg attached. + MIPSGPReg mipsReg; // if -1, no mipsreg attached. bool isDirty; // Should the register be written back? }; @@ -83,39 +80,39 @@ public: // Protect the arm register containing a MIPS register from spilling, to ensure that // it's being kept allocated. - void SpillLock(MIPSReg reg, MIPSReg reg2 = -1, MIPSReg reg3 = -1, MIPSReg reg4 = -1); - void ReleaseSpillLock(MIPSReg reg); + void SpillLock(MIPSGPReg reg, MIPSGPReg reg2 = MIPS_REG_INVALID, MIPSGPReg reg3 = MIPS_REG_INVALID, MIPSGPReg reg4 = MIPS_REG_INVALID); + void ReleaseSpillLock(MIPSGPReg reg); void ReleaseSpillLocks(); - void SetImm(MIPSReg reg, u32 immVal); - bool IsImm(MIPSReg reg) const; - u32 GetImm(MIPSReg reg) const; + void SetImm(MIPSGPReg reg, u32 immVal); + bool IsImm(MIPSGPReg reg) const; + u32 GetImm(MIPSGPReg reg) const; // Returns an ARM register containing the requested MIPS register. - ARMReg MapReg(MIPSReg reg, int mapFlags = 0); - ARMReg MapRegAsPointer(MIPSReg reg); // read-only, non-dirty. + ARMReg MapReg(MIPSGPReg reg, int mapFlags = 0); + ARMReg MapRegAsPointer(MIPSGPReg reg); // read-only, non-dirty. - bool IsMappedAsPointer(MIPSReg reg); + bool IsMappedAsPointer(MIPSGPReg reg); - void MapInIn(MIPSReg rd, MIPSReg rs); - void MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad = true); - void MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad = true); - void MapDirtyDirtyInIn(MIPSReg rd1, MIPSReg rd2, MIPSReg rs, MIPSReg rt, bool avoidLoad = true); + void MapInIn(MIPSGPReg rd, MIPSGPReg rs); + void MapDirtyIn(MIPSGPReg rd, MIPSGPReg rs, bool avoidLoad = true); + void MapDirtyInIn(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad = true); + void MapDirtyDirtyInIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad = true); void FlushArmReg(ARMReg r); - void FlushR(MIPSReg r); + void FlushR(MIPSGPReg r); void FlushBeforeCall(); void FlushAll(); - void DiscardR(MIPSReg r); + void DiscardR(MIPSGPReg r); - ARMReg R(int preg); // Returns a cached register, while checking that it's NOT mapped as a pointer - ARMReg RPtr(int preg); // Returns a cached register, while checking that it's mapped as a pointer + ARMReg R(MIPSGPReg preg); // Returns a cached register, while checking that it's NOT mapped as a pointer + ARMReg RPtr(MIPSGPReg preg); // Returns a cached register, while checking that it's mapped as a pointer void SetEmitter(ARMXEmitter *emitter) { emit_ = emitter; } // For better log output only. void SetCompilerPC(u32 compilerPC) { compilerPC_ = compilerPC; } - int GetMipsRegOffset(MIPSReg r); + int GetMipsRegOffset(MIPSGPReg r); private: const ARMReg *GetMIPSAllocationOrder(int &count); diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.h b/Core/MIPS/ARM/ArmRegCacheFPU.h index 8bca881110..13ef972159 100644 --- a/Core/MIPS/ARM/ArmRegCacheFPU.h +++ b/Core/MIPS/ARM/ArmRegCacheFPU.h @@ -134,7 +134,7 @@ private: NUM_MIPSFPUREG = TOTAL_MAPPABLE_MIPSFPUREGS, }; - RegARM ar[NUM_ARMFPUREG]; + FPURegARM ar[NUM_ARMFPUREG]; FPURegMIPS mr[NUM_MIPSFPUREG]; FPURegMIPS *vr; }; diff --git a/Core/MIPS/MIPS.h b/Core/MIPS/MIPS.h index 3fc6dbef49..7f311e8cb4 100644 --- a/Core/MIPS/MIPS.h +++ b/Core/MIPS/MIPS.h @@ -64,6 +64,10 @@ enum MIPSGPReg // ID for mipscall "callback" is stored here - from JPCSP MIPS_REG_CALL_ID=MIPS_REG_S0, MIPS_REG_INVALID=-1, + + // Not real regs, just for convenience/jit mapping. + MIPS_REG_HI = 32, + MIPS_REG_LO = 33, }; enum