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riscv: Stub out more IR compilation categories.

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Unknown W. Brackets committed 2023-07-23 18:01:00 -07:00
1 parent 05a2789cf4
commit c2da7d18bb
8 files changed
+836 -14
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Core/MIPS/RiscV/RiscVCompSystem.cpp
+73
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@@ -42,6 +42,10 @@ void RiscVJit::CompIR_Basic(IRInst inst) {
gpr.SetImm(inst.dest, inst.constant);
break;
case IROp::SetConstF:
CompIR_Generic(inst);
break;
case IROp::Downcount:
if (inst.constant <= 2048) {
ADDI(DOWNCOUNTREG, DOWNCOUNTREG, -(s32)inst.constant);
@@ -67,4 +71,73 @@ void RiscVJit::CompIR_Basic(IRInst inst) {
}
}
void RiscVJit::CompIR_Transfer(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::SetCtrlVFPU:
case IROp::SetCtrlVFPUReg:
case IROp::SetCtrlVFPUFReg:
case IROp::FpCondToReg:
case IROp::VfpuCtrlToReg:
case IROp::FMovFromGPR:
case IROp::FMovToGPR:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void RiscVJit::CompIR_System(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Interpret:
case IROp::Syscall:
case IROp::CallReplacement:
case IROp::Break:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void RiscVJit::CompIR_Breakpoint(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Breakpoint:
case IROp::MemoryCheck:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void RiscVJit::CompIR_ValidateAddress(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::ValidateAddress8:
case IROp::ValidateAddress16:
case IROp::ValidateAddress32:
case IROp::ValidateAddress128:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
} // namespace MIPSComp