diff --git a/Core/MIPS/RiscV/RiscVCompALU.cpp b/Core/MIPS/RiscV/RiscVCompALU.cpp
index 125c74fa51..2e4a7a248b 100644
--- a/Core/MIPS/RiscV/RiscVCompALU.cpp
+++ b/Core/MIPS/RiscV/RiscVCompALU.cpp
@@ -147,6 +147,16 @@ void RiscVJit::CompIR_Assign(IRInst inst) {
 		}
 		break;
 
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_Bits(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
 	case IROp::ReverseBits:
 		CompIR_Generic(inst);
 		break;
@@ -168,6 +178,116 @@ void RiscVJit::CompIR_Assign(IRInst inst) {
 		}
 		break;
 
+	case IROp::Clz:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_Shift(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Shl:
+	case IROp::Shr:
+	case IROp::Sar:
+	case IROp::Ror:
+	case IROp::ShlImm:
+	case IROp::ShrImm:
+	case IROp::SarImm:
+	case IROp::RorImm:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_Compare(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Slt:
+	case IROp::SltConst:
+	case IROp::SltU:
+	case IROp::SltUConst:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_CondAssign(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::MovZ:
+	case IROp::MovNZ:
+	case IROp::Max:
+	case IROp::Min:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_HiLo(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::MtLo:
+	case IROp::MtHi:
+	case IROp::MfLo:
+	case IROp::MfHi:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_Mult(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Mult:
+	case IROp::MultU:
+	case IROp::Madd:
+	case IROp::MaddU:
+	case IROp::Msub:
+	case IROp::MsubU:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_Div(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Div:
+	case IROp::DivU:
+		CompIR_Generic(inst);
+		break;
+
 	default:
 		INVALIDOP;
 		break;
diff --git a/Core/MIPS/RiscV/RiscVCompBranch.cpp b/Core/MIPS/RiscV/RiscVCompBranch.cpp
index 6e158cfc0d..a14ee49d0c 100644
--- a/Core/MIPS/RiscV/RiscVCompBranch.cpp
+++ b/Core/MIPS/RiscV/RiscVCompBranch.cpp
@@ -42,11 +42,6 @@ void RiscVJit::CompIR_Exit(IRInst inst) {
 	switch (inst.op) {
 	case IROp::ExitToConst:
 	case IROp::ExitToReg:
-	case IROp::ExitToConstIfEq:
-	case IROp::ExitToConstIfNeq:
-	case IROp::ExitToConstIfGeZ:
-	case IROp::ExitToConstIfLtZ:
-	case IROp::ExitToConstIfLeZ:
 	case IROp::ExitToPC:
 		CompIR_Generic(inst);
 		break;
@@ -57,4 +52,27 @@ void RiscVJit::CompIR_Exit(IRInst inst) {
 	}
 }
 
+void RiscVJit::CompIR_ExitIf(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	// Will probably always want this?
+	FlushAll();
+	switch (inst.op) {
+	case IROp::ExitToConstIfEq:
+	case IROp::ExitToConstIfNeq:
+	case IROp::ExitToConstIfGtZ:
+	case IROp::ExitToConstIfGeZ:
+	case IROp::ExitToConstIfLtZ:
+	case IROp::ExitToConstIfLeZ:
+	case IROp::ExitToConstIfFpTrue:
+	case IROp::ExitToConstIfFpFalse:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
 } // namespace MIPSComp
diff --git a/Core/MIPS/RiscV/RiscVCompFPU.cpp b/Core/MIPS/RiscV/RiscVCompFPU.cpp
index 61fb11d0e0..ef8e6a8db8 100644
--- a/Core/MIPS/RiscV/RiscVCompFPU.cpp
+++ b/Core/MIPS/RiscV/RiscVCompFPU.cpp
@@ -34,4 +34,153 @@ namespace MIPSComp {
 using namespace RiscVGen;
 using namespace RiscVJitConstants;
 
+void RiscVJit::CompIR_FArith(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::FAdd:
+	case IROp::FSub:
+	case IROp::FMul:
+	case IROp::FDiv:
+	case IROp::FSqrt:
+	case IROp::FNeg:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_FCondAssign(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::FMin:
+	case IROp::FMax:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_FAssign(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::FMov:
+	case IROp::FAbs:
+	case IROp::FSign:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_FRound(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::FRound:
+	case IROp::FTrunc:
+	case IROp::FCeil:
+	case IROp::FFloor:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_FCvt(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::FCvtWS:
+	case IROp::FCvtSW:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_FSat(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::FSat0_1:
+	case IROp::FSatMinus1_1:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_FCompare(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::ZeroFpCond:
+	case IROp::FCmp:
+	case IROp::FCmovVfpuCC:
+	case IROp::FCmpVfpuBit:
+	case IROp::FCmpVfpuAggregate:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_RoundingMode(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::RestoreRoundingMode:
+	case IROp::ApplyRoundingMode:
+	case IROp::UpdateRoundingMode:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_FSpecial(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::FSin:
+	case IROp::FCos:
+	case IROp::FRSqrt:
+	case IROp::FRecip:
+	case IROp::FAsin:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
 } // namespace MIPSComp
diff --git a/Core/MIPS/RiscV/RiscVCompLoadStore.cpp b/Core/MIPS/RiscV/RiscVCompLoadStore.cpp
index 11b19b0c35..13c9437fa4 100644
--- a/Core/MIPS/RiscV/RiscVCompLoadStore.cpp
+++ b/Core/MIPS/RiscV/RiscVCompLoadStore.cpp
@@ -34,4 +34,124 @@ namespace MIPSComp {
 using namespace RiscVGen;
 using namespace RiscVJitConstants;
 
+void RiscVJit::CompIR_Load(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Load8:
+	case IROp::Load8Ext:
+	case IROp::Load16:
+	case IROp::Load16Ext:
+	case IROp::Load32:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_LoadShift(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Load32Left:
+	case IROp::Load32Right:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_FLoad(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::LoadFloat:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_VecLoad(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::LoadVec4:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_Store(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Store8:
+	case IROp::Store16:
+	case IROp::Store32:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_StoreShift(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Store32Left:
+	case IROp::Store32Right:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_FStore(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::StoreFloat:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_VecStore(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::StoreVec4:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
 } // namespace MIPSComp
diff --git a/Core/MIPS/RiscV/RiscVCompSystem.cpp b/Core/MIPS/RiscV/RiscVCompSystem.cpp
index b5e5af3b24..d097915d0c 100644
--- a/Core/MIPS/RiscV/RiscVCompSystem.cpp
+++ b/Core/MIPS/RiscV/RiscVCompSystem.cpp
@@ -42,6 +42,10 @@ void RiscVJit::CompIR_Basic(IRInst inst) {
 		gpr.SetImm(inst.dest, inst.constant);
 		break;
 
+	case IROp::SetConstF:
+		CompIR_Generic(inst);
+		break;
+
 	case IROp::Downcount:
 		if (inst.constant <= 2048) {
 			ADDI(DOWNCOUNTREG, DOWNCOUNTREG, -(s32)inst.constant);
@@ -67,4 +71,73 @@ void RiscVJit::CompIR_Basic(IRInst inst) {
 	}
 }
 
+void RiscVJit::CompIR_Transfer(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::SetCtrlVFPU:
+	case IROp::SetCtrlVFPUReg:
+	case IROp::SetCtrlVFPUFReg:
+	case IROp::FpCondToReg:
+	case IROp::VfpuCtrlToReg:
+	case IROp::FMovFromGPR:
+	case IROp::FMovToGPR:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_System(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Interpret:
+	case IROp::Syscall:
+	case IROp::CallReplacement:
+	case IROp::Break:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_Breakpoint(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Breakpoint:
+	case IROp::MemoryCheck:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_ValidateAddress(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::ValidateAddress8:
+	case IROp::ValidateAddress16:
+	case IROp::ValidateAddress32:
+	case IROp::ValidateAddress128:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
 } // namespace MIPSComp
diff --git a/Core/MIPS/RiscV/RiscVCompVec.cpp b/Core/MIPS/RiscV/RiscVCompVec.cpp
index 8ccc3f129a..ac54192dd9 100644
--- a/Core/MIPS/RiscV/RiscVCompVec.cpp
+++ b/Core/MIPS/RiscV/RiscVCompVec.cpp
@@ -34,4 +34,90 @@ namespace MIPSComp {
 using namespace RiscVGen;
 using namespace RiscVJitConstants;
 
+void RiscVJit::CompIR_VecAssign(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Vec4Init:
+	case IROp::Vec4Shuffle:
+	case IROp::Vec4Mov:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_VecArith(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Vec4Add:
+	case IROp::Vec4Sub:
+	case IROp::Vec4Mul:
+	case IROp::Vec4Div:
+	case IROp::Vec4Scale:
+	case IROp::Vec4Neg:
+	case IROp::Vec4Abs:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_VecHoriz(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Vec4Dot:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_VecPack(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Vec2Unpack16To31:
+	case IROp::Vec2Unpack16To32:
+	case IROp::Vec4Unpack8To32:
+	case IROp::Vec4DuplicateUpperBitsAndShift1:
+	case IROp::Vec4Pack31To8:
+	case IROp::Vec4Pack32To8:
+	case IROp::Vec2Pack31To16:
+	case IROp::Vec2Pack32To16:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void RiscVJit::CompIR_VecClamp(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Vec4ClampToZero:
+	case IROp::Vec2ClampToZero:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
 } // namespace MIPSComp
diff --git a/Core/MIPS/RiscV/RiscVJit.cpp b/Core/MIPS/RiscV/RiscVJit.cpp
index 7736188706..0be5b5d59d 100644
--- a/Core/MIPS/RiscV/RiscVJit.cpp
+++ b/Core/MIPS/RiscV/RiscVJit.cpp
@@ -112,6 +112,7 @@ void RiscVJit::CompileIRInst(IRInst inst) {
 		break;
 
 	case IROp::SetConst:
+	case IROp::SetConstF:
 	case IROp::Downcount:
 	case IROp::SetPC:
 	case IROp::SetPCConst:
@@ -139,24 +140,245 @@ void RiscVJit::CompileIRInst(IRInst inst) {
 	case IROp::Mov:
 	case IROp::Ext8to32:
 	case IROp::Ext16to32:
+		CompIR_Assign(inst);
+		break;
+
 	case IROp::ReverseBits:
 	case IROp::BSwap16:
 	case IROp::BSwap32:
-		CompIR_Assign(inst);
+	case IROp::Clz:
+		CompIR_Bits(inst);
+		break;
+
+	case IROp::Shl:
+	case IROp::Shr:
+	case IROp::Sar:
+	case IROp::Ror:
+	case IROp::ShlImm:
+	case IROp::ShrImm:
+	case IROp::SarImm:
+	case IROp::RorImm:
+		CompIR_Shift(inst);
+		break;
+
+	case IROp::Slt:
+	case IROp::SltConst:
+	case IROp::SltU:
+	case IROp::SltUConst:
+		CompIR_Compare(inst);
+		break;
+
+	case IROp::MovZ:
+	case IROp::MovNZ:
+	case IROp::Max:
+	case IROp::Min:
+		CompIR_CondAssign(inst);
+		break;
+
+	case IROp::MtLo:
+	case IROp::MtHi:
+	case IROp::MfLo:
+	case IROp::MfHi:
+		CompIR_HiLo(inst);
+		break;
+
+	case IROp::Mult:
+	case IROp::MultU:
+	case IROp::Madd:
+	case IROp::MaddU:
+	case IROp::Msub:
+	case IROp::MsubU:
+		CompIR_Mult(inst);
+		break;
+
+	case IROp::Div:
+	case IROp::DivU:
+		CompIR_Div(inst);
+		break;
+
+	case IROp::Load8:
+	case IROp::Load8Ext:
+	case IROp::Load16:
+	case IROp::Load16Ext:
+	case IROp::Load32:
+		CompIR_Load(inst);
+		break;
+
+	case IROp::Load32Left:
+	case IROp::Load32Right:
+		CompIR_LoadShift(inst);
+		break;
+
+	case IROp::LoadFloat:
+		CompIR_FLoad(inst);
+		break;
+
+	case IROp::LoadVec4:
+		CompIR_VecLoad(inst);
+		break;
+
+	case IROp::Store8:
+	case IROp::Store16:
+	case IROp::Store32:
+		CompIR_Store(inst);
+		break;
+
+	case IROp::Store32Left:
+	case IROp::Store32Right:
+		CompIR_StoreShift(inst);
+		break;
+
+	case IROp::StoreFloat:
+		CompIR_FStore(inst);
+		break;
+
+	case IROp::StoreVec4:
+		CompIR_VecStore(inst);
+		break;
+
+	case IROp::FAdd:
+	case IROp::FSub:
+	case IROp::FMul:
+	case IROp::FDiv:
+	case IROp::FSqrt:
+	case IROp::FNeg:
+		CompIR_FArith(inst);
+		break;
+
+	case IROp::FMin:
+	case IROp::FMax:
+		CompIR_FCondAssign(inst);
+		break;
+
+	case IROp::FMov:
+	case IROp::FAbs:
+	case IROp::FSign:
+		CompIR_FAssign(inst);
+		break;
+
+	case IROp::FRound:
+	case IROp::FTrunc:
+	case IROp::FCeil:
+	case IROp::FFloor:
+		CompIR_FRound(inst);
+		break;
+
+	case IROp::FCvtWS:
+	case IROp::FCvtSW:
+		CompIR_FCvt(inst);
+		break;
+
+	case IROp::FSat0_1:
+	case IROp::FSatMinus1_1:
+		CompIR_FSat(inst);
+		break;
+
+	case IROp::ZeroFpCond:
+	case IROp::FCmp:
+	case IROp::FCmovVfpuCC:
+	case IROp::FCmpVfpuBit:
+	case IROp::FCmpVfpuAggregate:
+		CompIR_FCompare(inst);
+		break;
+
+	case IROp::RestoreRoundingMode:
+	case IROp::ApplyRoundingMode:
+	case IROp::UpdateRoundingMode:
+		CompIR_RoundingMode(inst);
+		break;
+
+	case IROp::SetCtrlVFPU:
+	case IROp::SetCtrlVFPUReg:
+	case IROp::SetCtrlVFPUFReg:
+	case IROp::FpCondToReg:
+	case IROp::VfpuCtrlToReg:
+	case IROp::FMovFromGPR:
+	case IROp::FMovToGPR:
+		CompIR_Transfer(inst);
+		break;
+
+	case IROp::Vec4Init:
+	case IROp::Vec4Shuffle:
+	case IROp::Vec4Mov:
+		CompIR_VecAssign(inst);
+		break;
+
+	case IROp::Vec4Add:
+	case IROp::Vec4Sub:
+	case IROp::Vec4Mul:
+	case IROp::Vec4Div:
+	case IROp::Vec4Scale:
+	case IROp::Vec4Neg:
+	case IROp::Vec4Abs:
+		CompIR_VecArith(inst);
+		break;
+
+	case IROp::Vec4Dot:
+		CompIR_VecHoriz(inst);
+		break;
+
+	case IROp::Vec2Unpack16To31:
+	case IROp::Vec2Unpack16To32:
+	case IROp::Vec4Unpack8To32:
+	case IROp::Vec4DuplicateUpperBitsAndShift1:
+	case IROp::Vec4Pack31To8:
+	case IROp::Vec4Pack32To8:
+	case IROp::Vec2Pack31To16:
+	case IROp::Vec2Pack32To16:
+		CompIR_VecPack(inst);
+		break;
+
+	case IROp::Vec4ClampToZero:
+	case IROp::Vec2ClampToZero:
+		CompIR_VecClamp(inst);
+		break;
+
+	case IROp::FSin:
+	case IROp::FCos:
+	case IROp::FRSqrt:
+	case IROp::FRecip:
+	case IROp::FAsin:
+		CompIR_FSpecial(inst);
+		break;
+
+	case IROp::Interpret:
+	case IROp::Syscall:
+	case IROp::CallReplacement:
+	case IROp::Break:
+		CompIR_System(inst);
+		break;
+
+	case IROp::Breakpoint:
+	case IROp::MemoryCheck:
+		CompIR_Breakpoint(inst);
+		break;
+
+	case IROp::ValidateAddress8:
+	case IROp::ValidateAddress16:
+	case IROp::ValidateAddress32:
+	case IROp::ValidateAddress128:
+		CompIR_ValidateAddress(inst);
 		break;
 
 	case IROp::ExitToConst:
 	case IROp::ExitToReg:
-	case IROp::ExitToConstIfEq:
-	case IROp::ExitToConstIfNeq:
-	case IROp::ExitToConstIfGeZ:
-	case IROp::ExitToConstIfLtZ:
-	case IROp::ExitToConstIfLeZ:
 	case IROp::ExitToPC:
 		CompIR_Exit(inst);
 		break;
 
+	case IROp::ExitToConstIfEq:
+	case IROp::ExitToConstIfNeq:
+	case IROp::ExitToConstIfGtZ:
+	case IROp::ExitToConstIfGeZ:
+	case IROp::ExitToConstIfLtZ:
+	case IROp::ExitToConstIfLeZ:
+	case IROp::ExitToConstIfFpTrue:
+	case IROp::ExitToConstIfFpFalse:
+		CompIR_ExitIf(inst);
+		break;
+
 	default:
+		_assert_msg_(false, "Unexpected IR op %d", (int)inst.op);
 		CompIR_Generic(inst);
 		break;
 	}
diff --git a/Core/MIPS/RiscV/RiscVJit.h b/Core/MIPS/RiscV/RiscVJit.h
index 1467d80b3e..d828d2ee56 100644
--- a/Core/MIPS/RiscV/RiscVJit.h
+++ b/Core/MIPS/RiscV/RiscVJit.h
@@ -63,12 +63,46 @@ private:
 
 	void FlushAll();
 
-	void CompIR_Generic(IRInst inst);
-	void CompIR_Basic(IRInst inst);
 	void CompIR_Arith(IRInst inst);
-	void CompIR_Logic(IRInst inst);
 	void CompIR_Assign(IRInst inst);
+	void CompIR_Basic(IRInst inst);
+	void CompIR_Bits(IRInst inst);
+	void CompIR_Breakpoint(IRInst inst);
+	void CompIR_Compare(IRInst inst);
+	void CompIR_CondAssign(IRInst inst);
+	void CompIR_Div(IRInst inst);
 	void CompIR_Exit(IRInst inst);
+	void CompIR_ExitIf(IRInst inst);
+	void CompIR_FArith(IRInst inst);
+	void CompIR_FAssign(IRInst inst);
+	void CompIR_FCompare(IRInst inst);
+	void CompIR_FCondAssign(IRInst inst);
+	void CompIR_FCvt(IRInst inst);
+	void CompIR_FLoad(IRInst inst);
+	void CompIR_FRound(IRInst inst);
+	void CompIR_FSat(IRInst inst);
+	void CompIR_FSpecial(IRInst inst);
+	void CompIR_FStore(IRInst inst);
+	void CompIR_Generic(IRInst inst);
+	void CompIR_HiLo(IRInst inst);
+	void CompIR_Load(IRInst inst);
+	void CompIR_LoadShift(IRInst inst);
+	void CompIR_Logic(IRInst inst);
+	void CompIR_Mult(IRInst inst);
+	void CompIR_RoundingMode(IRInst inst);
+	void CompIR_Shift(IRInst inst);
+	void CompIR_Store(IRInst inst);
+	void CompIR_StoreShift(IRInst inst);
+	void CompIR_System(IRInst inst);
+	void CompIR_Transfer(IRInst inst);
+	void CompIR_VecArith(IRInst inst);
+	void CompIR_VecAssign(IRInst inst);
+	void CompIR_VecClamp(IRInst inst);
+	void CompIR_VecHoriz(IRInst inst);
+	void CompIR_VecLoad(IRInst inst);
+	void CompIR_VecPack(IRInst inst);
+	void CompIR_VecStore(IRInst inst);
+	void CompIR_ValidateAddress(IRInst inst);
 
 	RiscVRegCache gpr;