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https://github.com/hrydgard/ppsspp.git
synced 2026-10-16 07:50:28 +02:00
A small optimization, a few jit stubs, and cross/quat product on x86.
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Henrik Rydgard committed
1 parent
61d419b2ec
commit
4e8958f42d
5 files changed
+143
-12
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@@ -1144,6 +1144,18 @@ namespace MIPSComp
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DISABLE;
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}
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void Jit::Comp_VCrossQuat(u32 op) {
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DISABLE;
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}
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void Jit::Comp_Vsge(u32 op) {
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DISABLE;
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}
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void Jit::Comp_Vslt(u32 op) {
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DISABLE;
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}
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void Jit::Comp_Vcmp(u32 op) {
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// Not ready yet
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DISABLE;
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@@ -222,6 +222,9 @@ public:
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void Comp_Vcmov(u32 op);
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void Comp_Viim(u32 op);
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void Comp_Vfim(u32 op);
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void Comp_VCrossQuat(u32 op);
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void Comp_Vsge(u32 op);
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void Comp_Vslt(u32 op);
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JitBlockCache *GetBlockCache() { return &blocks; }
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@@ -506,8 +506,8 @@ const MIPSInstruction tableVFPU3[8] = //011011 xxx
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INSTR("vmax",&Jit::Comp_VecDo3, Dis_VectorSet3, Int_Vminmax, IS_VFPU|OUT_EAT_PREFIX),
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{-2},
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INSTR("vscmp",&Jit::Comp_Generic, Dis_VectorSet3, Int_Vscmp, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vsge",&Jit::Comp_Generic, Dis_VectorSet3, Int_Vsge, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vslt",&Jit::Comp_Generic, Dis_VectorSet3, Int_Vslt, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vsge",&Jit::Comp_Vsge, Dis_VectorSet3, Int_Vsge, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vslt",&Jit::Comp_Vslt, Dis_VectorSet3, Int_Vslt, IS_VFPU|OUT_EAT_PREFIX),
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};
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@@ -651,10 +651,10 @@ const MIPSInstruction tableVFPU6[32] = //111100 xxx
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INSTR("vmscl",&Jit::Comp_Vmscl, Dis_Generic, Int_Vmscl, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vmscl",&Jit::Comp_Vmscl, Dis_Generic, Int_Vmscl, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vcrsp.t/vqmul.q",&Jit::Comp_Generic, Dis_CrossQuat, Int_CrossQuat, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vcrsp.t/vqmul.q",&Jit::Comp_Generic, Dis_CrossQuat, Int_CrossQuat, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vcrsp.t/vqmul.q",&Jit::Comp_Generic, Dis_CrossQuat, Int_CrossQuat, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vcrsp.t/vqmul.q",&Jit::Comp_Generic, Dis_CrossQuat, Int_CrossQuat, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vcrsp.t/vqmul.q",&Jit::Comp_VCrossQuat, Dis_CrossQuat, Int_CrossQuat, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vcrsp.t/vqmul.q",&Jit::Comp_VCrossQuat, Dis_CrossQuat, Int_CrossQuat, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vcrsp.t/vqmul.q",&Jit::Comp_VCrossQuat, Dis_CrossQuat, Int_CrossQuat, IS_VFPU|OUT_EAT_PREFIX),
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INSTR("vcrsp.t/vqmul.q",&Jit::Comp_VCrossQuat, Dis_CrossQuat, Int_CrossQuat, IS_VFPU|OUT_EAT_PREFIX),
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//24
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{-2},
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{-2},
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+119
-6
@@ -498,6 +498,114 @@ void Jit::Comp_VHdp(u32 op) {
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fpr.ReleaseSpillLocks();
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}
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void Jit::Comp_VCrossQuat(u32 op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix())
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DISABLE;
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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u8 sregs[4], tregs[4], dregs[4];
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GetVectorRegs(sregs, sz, _VS);
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GetVectorRegs(tregs, sz, _VT);
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GetVectorRegs(dregs, sz, _VD);
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if (sz == V_Triple) {
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// Cross product vcrsp.t
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fpr.MapRegsV(sregs, sz, 0);
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// Compute X
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MOVSS(XMM0, fpr.V(sregs[1]));
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MULSS(XMM0, fpr.V(tregs[2]));
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MOVSS(XMM1, fpr.V(sregs[2]));
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MULSS(XMM1, fpr.V(tregs[1]));
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SUBSS(XMM0, R(XMM1));
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MOVSS(fpr.V(dregs[0]), XMM0);
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// Compute Y
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MOVSS(XMM0, fpr.V(sregs[2]));
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MULSS(XMM0, fpr.V(tregs[0]));
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MOVSS(XMM1, fpr.V(sregs[0]));
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MULSS(XMM1, fpr.V(tregs[2]));
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SUBSS(XMM0, R(XMM1));
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MOVSS(fpr.V(dregs[1]), XMM0);
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// Compute Z
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MOVSS(XMM0, fpr.V(sregs[0]));
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MULSS(XMM0, fpr.V(tregs[1]));
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MOVSS(XMM1, fpr.V(sregs[1]));
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MULSS(XMM1, fpr.V(tregs[0]));
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SUBSS(XMM0, R(XMM1));
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MOVSS(fpr.V(dregs[2]), XMM0);
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} else if (sz == V_Quad) {
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// Quaternion product vqmul.q untested
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DISABLE;
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fpr.MapRegsV(sregs, sz, 0);
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// Compute X
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MOVSS(XMM0, fpr.V(sregs[0]));
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MULSS(XMM0, fpr.V(tregs[3]));
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MOVSS(XMM1, fpr.V(sregs[1]));
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MULSS(XMM1, fpr.V(tregs[2]));
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ADDSS(XMM0, R(XMM1));
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MOVSS(XMM1, fpr.V(sregs[2]));
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MULSS(XMM1, fpr.V(tregs[1]));
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SUBSS(XMM0, R(XMM1));
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MOVSS(XMM1, fpr.V(sregs[3]));
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MULSS(XMM1, fpr.V(tregs[0]));
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ADDSS(XMM0, R(XMM1));
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MOVSS(fpr.V(dregs[0]), XMM0);
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// Compute Y
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MOVSS(XMM0, fpr.V(sregs[1]));
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MULSS(XMM0, fpr.V(tregs[3]));
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MOVSS(XMM1, fpr.V(sregs[2]));
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MULSS(XMM1, fpr.V(tregs[0]));
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ADDSS(XMM0, R(XMM1));
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MOVSS(XMM1, fpr.V(sregs[3]));
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MULSS(XMM1, fpr.V(tregs[1]));
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ADDSS(XMM0, R(XMM1));
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MOVSS(XMM1, fpr.V(sregs[0]));
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MULSS(XMM1, fpr.V(tregs[2]));
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SUBSS(XMM0, R(XMM1));
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MOVSS(fpr.V(dregs[1]), XMM0);
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// Compute Z
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MOVSS(XMM0, fpr.V(sregs[0]));
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MULSS(XMM0, fpr.V(tregs[1]));
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MOVSS(XMM1, fpr.V(sregs[1]));
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MULSS(XMM1, fpr.V(tregs[0]));
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SUBSS(XMM0, R(XMM1));
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MOVSS(XMM1, fpr.V(sregs[2]));
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MULSS(XMM1, fpr.V(tregs[3]));
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ADDSS(XMM0, R(XMM1));
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MOVSS(XMM1, fpr.V(sregs[3]));
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MULSS(XMM1, fpr.V(tregs[2]));
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ADDSS(XMM0, R(XMM1));
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MOVSS(fpr.V(dregs[2]), XMM0);
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// Compute W
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MOVSS(XMM0, fpr.V(sregs[3]));
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MULSS(XMM0, fpr.V(tregs[3]));
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MOVSS(XMM1, fpr.V(sregs[1]));
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MULSS(XMM1, fpr.V(tregs[1]));
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SUBSS(XMM0, R(XMM1));
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MOVSS(XMM1, fpr.V(sregs[2]));
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MULSS(XMM1, fpr.V(tregs[2]));
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ADDSS(XMM0, R(XMM1));
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MOVSS(XMM1, fpr.V(sregs[0]));
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MULSS(XMM1, fpr.V(tregs[0]));
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SUBSS(XMM0, R(XMM1));
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MOVSS(fpr.V(dregs[3]), XMM0);
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}
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fpr.ReleaseSpillLocks();
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}
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void Jit::Comp_VecDo3(u32 op) {
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CONDITIONAL_DISABLE;
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@@ -660,7 +768,7 @@ void Jit::Comp_Vcmp(u32 op) {
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break;
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case VC_TR: // c = 1; break;
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MOV(32, R(ECX), Imm32(1));
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MOV(32, R(ECX), Imm32(1 << i));
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break;
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case VC_EQ: // c = s[i] == t[i]; break;
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@@ -724,16 +832,14 @@ void Jit::Comp_Vcmp(u32 op) {
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if (compareTwo || compareToZero) {
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MOVSS(M((void *) &ssCompareTemp), XMM1);
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MOV(32, R(ECX), M((void *) &ssCompareTemp));
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AND(32, R(ECX), Imm32(1));
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AND(32, R(ECX), Imm32(1 << i));
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}
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if (i > 0) {
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SHL(32, R(ECX), Imm8(i));
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}
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if (i == 0)
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MOV(32, R(EAX), R(ECX));
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else
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OR(32, R(EAX), R(ECX));
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affected_bits |= 1 << i;
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}
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@@ -1332,7 +1438,6 @@ void Jit::Comp_Vtfm(u32 op) {
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fpr.ReleaseSpillLocks();
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}
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void Jit::Comp_VCrs(u32 op) {
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DISABLE;
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}
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@@ -1361,6 +1466,14 @@ void Jit::Comp_Vcmov(u32 op) {
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DISABLE;
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}
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void Jit::Comp_Vsge(u32 op) {
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DISABLE;
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}
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void Jit::Comp_Vslt(u32 op) {
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DISABLE;
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}
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void Jit::Comp_Viim(u32 op) {
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CONDITIONAL_DISABLE;
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@@ -228,6 +228,9 @@ public:
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void Comp_Vcmov(u32 op);
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void Comp_Viim(u32 op);
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void Comp_Vfim(u32 op);
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void Comp_VCrossQuat(u32 op);
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void Comp_Vsge(u32 op);
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void Comp_Vslt(u32 op);
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void Comp_DoNothing(u32 op);
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