Make all the Comp_Cache implementations the same.

We have the informative comments in the interpreter implementation
anyway.

Core/MIPS/IR/IRCompLoadStore.cpp

@@ -108,37 +108,17 @@ namespace MIPSComp {
 	void IRFrontend::Comp_Cache(MIPSOpcode op) {
 		CONDITIONAL_DISABLE(LSU);
 
-//		int imm = (s16)(op & 0xFFFF);
-//		int rs = _RS;
-//		int addr = R(rs) + imm;
 		int func = (op >> 16) & 0x1F;
 
-		// It appears that a cache line is 0x40 (64) bytes, loops in games
-		// issue the cache instruction at that interval.
-
-		// These codes might be PSP-specific, they don't match regular MIPS cache codes very well
+		// See Int_Cache for the definitions.
 		switch (func) {
-			// Icache
-		case 8:
-			// Invalidate the instruction cache at this address
-			DISABLE;
-			break;
-			// Dcache
-		case 24:
-			// "Create Dirty Exclusive" - for avoiding a cacheline fill before writing to it.
-			// Will cause garbage on the real machine so we just ignore it, the app will overwrite the cacheline.
-			break;
-		case 25:  // Hit Invalidate - zaps the line if present in cache. Should not writeback???? scary.
-			// No need to do anything.
-			break;
-		case 27:  // D-cube. Hit Writeback Invalidate.  Tony Hawk Underground 2
-			break;
-		case 30:  // GTA LCS, a lot. Fill (prefetch).   Tony Hawk Underground 2
-			break;
-
+		case 24: break;
+		case 25: break;
+		case 27: break;
+		case 30: break;
 		default:
+			// Fall back to the interpreter.
 			DISABLE;
-			break;
 		}
 	}
 }