From 4c034ce988cde30fd82a161a76fbaa0545fc0387 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= Date: Fri, 16 Oct 2020 09:13:41 +0200 Subject: [PATCH] Make all the Comp_Cache implementations the same. We have the informative comments in the interpreter implementation anyway. --- Core/MIPS/ARM/ArmCompLoadStore.cpp | 34 ++++++-------------------- Core/MIPS/ARM64/Arm64CompLoadStore.cpp | 34 ++++++-------------------- Core/MIPS/IR/IRCompLoadStore.cpp | 32 +++++------------------- Core/MIPS/MIPSInt.cpp | 2 ++ Core/MIPS/x86/CompLoadStore.cpp | 15 +++++++++++- 5 files changed, 38 insertions(+), 79 deletions(-) diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp index 3d49b2dc61..96c8f7133b 100644 --- a/Core/MIPS/ARM/ArmCompLoadStore.cpp +++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp @@ -386,37 +386,19 @@ namespace MIPSComp } void ArmJit::Comp_Cache(MIPSOpcode op) { - // int imm = (s16)(op & 0xFFFF); - // int rs = _RS; - // int addr = R(rs) + imm; + CONDITIONAL_DISABLE(LSU); + int func = (op >> 16) & 0x1F; - // It appears that a cache line is 0x40 (64) bytes, loops in games - // issue the cache instruction at that interval. - - // These codes might be PSP-specific, they don't match regular MIPS cache codes very well + // See Int_Cache for the definitions. switch (func) { - // Icache - case 8: - // Invalidate the instruction cache at this address - DISABLE; - break; - // Dcache - case 24: - // "Create Dirty Exclusive" - for avoiding a cacheline fill before writing to it. - // Will cause garbage on the real machine so we just ignore it, the app will overwrite the cacheline. - break; - case 25: // Hit Invalidate - zaps the line if present in cache. Should not writeback???? scary. - // No need to do anything. - break; - case 27: // D-cube. Hit Writeback Invalidate. Tony Hawk Underground 2 - break; - case 30: // GTA LCS, a lot. Fill (prefetch). Tony Hawk Underground 2 - break; - + case 24: break; + case 25: break; + case 27: break; + case 30: break; default: + // Fall back to the interpreter. DISABLE; - break; } } } diff --git a/Core/MIPS/ARM64/Arm64CompLoadStore.cpp b/Core/MIPS/ARM64/Arm64CompLoadStore.cpp index ad706c5221..ca1aae8a8a 100644 --- a/Core/MIPS/ARM64/Arm64CompLoadStore.cpp +++ b/Core/MIPS/ARM64/Arm64CompLoadStore.cpp @@ -432,37 +432,19 @@ namespace MIPSComp { } void Arm64Jit::Comp_Cache(MIPSOpcode op) { - // int imm = (s16)(op & 0xFFFF); - // int rs = _RS; - // int addr = R(rs) + imm; + CONDITIONAL_DISABLE(LSU); + int func = (op >> 16) & 0x1F; - // It appears that a cache line is 0x40 (64) bytes, loops in games - // issue the cache instruction at that interval. - - // These codes might be PSP-specific, they don't match regular MIPS cache codes very well + // See Int_Cache for the definitions. switch (func) { - // Icache - case 8: - // Invalidate the instruction cache at this address - DISABLE; - break; - // Dcache - case 24: - // "Create Dirty Exclusive" - for avoiding a cacheline fill before writing to it. - // Will cause garbage on the real machine so we just ignore it, the app will overwrite the cacheline. - break; - case 25: // Hit Invalidate - zaps the line if present in cache. Should not writeback???? scary. - // No need to do anything. - break; - case 27: // D-cube. Hit Writeback Invalidate. Tony Hawk Underground 2 - break; - case 30: // GTA LCS, a lot. Fill (prefetch). Tony Hawk Underground 2 - break; - + case 24: break; + case 25: break; + case 27: break; + case 30: break; default: + // Fall back to the interpreter. DISABLE; - break; } } } diff --git a/Core/MIPS/IR/IRCompLoadStore.cpp b/Core/MIPS/IR/IRCompLoadStore.cpp index a8ed9d8166..ec2fc33aaf 100644 --- a/Core/MIPS/IR/IRCompLoadStore.cpp +++ b/Core/MIPS/IR/IRCompLoadStore.cpp @@ -108,37 +108,17 @@ namespace MIPSComp { void IRFrontend::Comp_Cache(MIPSOpcode op) { CONDITIONAL_DISABLE(LSU); -// int imm = (s16)(op & 0xFFFF); -// int rs = _RS; -// int addr = R(rs) + imm; int func = (op >> 16) & 0x1F; - // It appears that a cache line is 0x40 (64) bytes, loops in games - // issue the cache instruction at that interval. - - // These codes might be PSP-specific, they don't match regular MIPS cache codes very well + // See Int_Cache for the definitions. switch (func) { - // Icache - case 8: - // Invalidate the instruction cache at this address - DISABLE; - break; - // Dcache - case 24: - // "Create Dirty Exclusive" - for avoiding a cacheline fill before writing to it. - // Will cause garbage on the real machine so we just ignore it, the app will overwrite the cacheline. - break; - case 25: // Hit Invalidate - zaps the line if present in cache. Should not writeback???? scary. - // No need to do anything. - break; - case 27: // D-cube. Hit Writeback Invalidate. Tony Hawk Underground 2 - break; - case 30: // GTA LCS, a lot. Fill (prefetch). Tony Hawk Underground 2 - break; - + case 24: break; + case 25: break; + case 27: break; + case 30: break; default: + // Fall back to the interpreter. DISABLE; - break; } } } diff --git a/Core/MIPS/MIPSInt.cpp b/Core/MIPS/MIPSInt.cpp index bfbce5db51..0065774933 100644 --- a/Core/MIPS/MIPSInt.cpp +++ b/Core/MIPS/MIPSInt.cpp @@ -102,6 +102,8 @@ namespace MIPSInt // issue the cache instruction at that interval. // These codes might be PSP-specific, they don't match regular MIPS cache codes very well + + // NOTE: If you add support for more, make sure they are handled in the various Jit::Comp_Cache. switch (func) { // Icache case 8: diff --git a/Core/MIPS/x86/CompLoadStore.cpp b/Core/MIPS/x86/CompLoadStore.cpp index e3d87bcf94..f094684417 100644 --- a/Core/MIPS/x86/CompLoadStore.cpp +++ b/Core/MIPS/x86/CompLoadStore.cpp @@ -401,7 +401,20 @@ namespace MIPSComp { } void Jit::Comp_Cache(MIPSOpcode op) { - DISABLE; + CONDITIONAL_DISABLE(LSU); + + int func = (op >> 16) & 0x1F; + + // See Int_Cache for the definitions. + switch (func) { + case 24: break; + case 25: break; + case 27: break; + case 30: break; + default: + // Fall back to the interpreter. + DISABLE; + } } }