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irjit: ZeroFpCond -> FpCondFromReg.

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We already have a zero reg, so this is more useful and symmetrical.
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Unknown W. Brackets committed 2023-08-13 10:40:47 -07:00
1 parent 50ea506b6a
commit 2b36e0a625
8 files changed
+18 -15
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Core/MIPS/RiscV/RiscVCompSystem.cpp
+5 -4
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@@ -105,16 +105,17 @@ void RiscVJitBackend::CompIR_Transfer(IRInst inst) {
FMV(FMv::X, FMv::W, gpr.R(IRREG_VFPU_CTRL_BASE + inst.dest), fpr.R(inst.src1));
break;
case IROp::FpCondFromReg:
gpr.MapDirtyIn(IRREG_FPCOND, inst.src1);
MV(gpr.R(IRREG_FPCOND), gpr.R(inst.src1));
break;
case IROp::FpCondToReg:
gpr.MapDirtyIn(inst.dest, IRREG_FPCOND);
MV(gpr.R(inst.dest), gpr.R(IRREG_FPCOND));
gpr.MarkDirty(gpr.R(inst.dest), gpr.IsNormalized32(IRREG_FPCOND));
break;
case IROp::ZeroFpCond:
gpr.SetImm(IRREG_FPCOND, 0);
break;
case IROp::FpCtrlFromReg:
gpr.MapDirtyIn(IRREG_FPCOND, inst.src1, MapType::AVOID_LOAD_MARK_NORM32);
LI(SCRATCH1, 0x0181FFFF);