diff --git a/Core/MIPS/IR/IRCompFPU.cpp b/Core/MIPS/IR/IRCompFPU.cpp
index 3c3ed87d03..e83f3a709f 100644
--- a/Core/MIPS/IR/IRCompFPU.cpp
+++ b/Core/MIPS/IR/IRCompFPU.cpp
@@ -102,7 +102,7 @@ void IRFrontend::Comp_FPUComp(MIPSOpcode op) {
 	int opc = op & 0xF;
 	if (opc >= 8) opc -= 8; // alias
 	if (opc == 0) {  // f, sf (signalling false)
-		ir.Write(IROp::ZeroFpCond);
+		ir.Write(IROp::FpCondFromReg, 0, MIPS_REG_ZERO);
 		return;
 	}
 
diff --git a/Core/MIPS/IR/IRInst.cpp b/Core/MIPS/IR/IRInst.cpp
index 5cdfc3824a..bc7d9f4a9a 100644
--- a/Core/MIPS/IR/IRInst.cpp
+++ b/Core/MIPS/IR/IRInst.cpp
@@ -113,7 +113,7 @@ static const IRMeta irMeta[] = {
 	{ IROp::FSatMinus1_1, "FSat(-1 - 1)", "FF" },
 	{ IROp::FMovFromGPR, "FMovFromGPR", "FG" },
 	{ IROp::FMovToGPR, "FMovToGPR", "GF" },
-	{ IROp::ZeroFpCond, "ZeroFpCond", "" },
+	{ IROp::FpCondFromReg, "FpCondFromReg", "_G" },
 	{ IROp::FpCondToReg, "FpCondToReg", "G" },
 	{ IROp::FpCtrlFromReg, "FpCtrlFromReg", "_G" },
 	{ IROp::FpCtrlToReg, "FpCtrlToReg", "G" },
diff --git a/Core/MIPS/IR/IRInst.h b/Core/MIPS/IR/IRInst.h
index f626204791..dd93ed823b 100644
--- a/Core/MIPS/IR/IRInst.h
+++ b/Core/MIPS/IR/IRInst.h
@@ -138,12 +138,12 @@ enum class IROp : u8 {
 	FSat0_1,
 	FSatMinus1_1,
 
+	FpCondFromReg,
 	FpCondToReg,
 	FpCtrlFromReg,
 	FpCtrlToReg,
 	VfpuCtrlToReg,
 
-	ZeroFpCond,
 	FCmp,
 
 	FCmovVfpuCC,
diff --git a/Core/MIPS/IR/IRInterpreter.cpp b/Core/MIPS/IR/IRInterpreter.cpp
index fd5ecf7a13..1beed06f8d 100644
--- a/Core/MIPS/IR/IRInterpreter.cpp
+++ b/Core/MIPS/IR/IRInterpreter.cpp
@@ -850,6 +850,9 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
 			break;
 		}
 
+		case IROp::FpCondFromReg:
+			mips->fpcond = mips->r[inst->dest];
+			break;
 		case IROp::FpCondToReg:
 			mips->r[inst->dest] = mips->fpcond;
 			break;
@@ -1001,10 +1004,6 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
 			break;
 		}
 
-		case IROp::ZeroFpCond:
-			mips->fpcond = 0;
-			break;
-
 		case IROp::FMovFromGPR:
 			memcpy(&mips->f[inst->dest], &mips->r[inst->src1], 4);
 			break;
diff --git a/Core/MIPS/IR/IRNativeCommon.cpp b/Core/MIPS/IR/IRNativeCommon.cpp
index 523849e376..a8ec952737 100644
--- a/Core/MIPS/IR/IRNativeCommon.cpp
+++ b/Core/MIPS/IR/IRNativeCommon.cpp
@@ -287,8 +287,8 @@ void IRNativeBackend::CompileIRInst(IRInst inst) {
 	case IROp::SetCtrlVFPU:
 	case IROp::SetCtrlVFPUReg:
 	case IROp::SetCtrlVFPUFReg:
+	case IROp::FpCondFromReg:
 	case IROp::FpCondToReg:
-	case IROp::ZeroFpCond:
 	case IROp::FpCtrlFromReg:
 	case IROp::FpCtrlToReg:
 	case IROp::VfpuCtrlToReg:
diff --git a/Core/MIPS/IR/IRPassSimplify.cpp b/Core/MIPS/IR/IRPassSimplify.cpp
index beecf7264e..577f80579e 100644
--- a/Core/MIPS/IR/IRPassSimplify.cpp
+++ b/Core/MIPS/IR/IRPassSimplify.cpp
@@ -740,6 +740,10 @@ bool PropagateConstants(const IRWriter &in, IRWriter &out, const IROptions &opts
 			out.Write(inst);
 			break;
 
+		case IROp::FpCondFromReg:
+			gpr.MapDirtyIn(IRREG_FPCOND, inst.src1);
+			out.Write(inst);
+			break;
 		case IROp::FpCondToReg:
 			if (gpr.IsImm(IRREG_FPCOND)) {
 				gpr.SetImm(inst.dest, gpr.GetImm(IRREG_FPCOND));
@@ -779,7 +783,6 @@ bool PropagateConstants(const IRWriter &in, IRWriter &out, const IROptions &opts
 			out.Write(inst);
 			break;
 
-		case IROp::ZeroFpCond:
 		case IROp::FCmp:
 			gpr.MapDirty(IRREG_FPCOND);
 			goto doDefault;
@@ -1383,6 +1386,7 @@ bool ReorderLoadStore(const IRWriter &in, IRWriter &out, const IROptions &opts)
 
 		case IROp::MtHi:
 		case IROp::MtLo:
+		case IROp::FpCondFromReg:
 			if (inst.src1 && otherRegs[inst.src1] != RegState::CHANGED)
 				otherRegs[inst.src1] = RegState::READ;
 			otherQueue.push_back(inst);
@@ -1391,7 +1395,6 @@ bool ReorderLoadStore(const IRWriter &in, IRWriter &out, const IROptions &opts)
 
 		case IROp::Nop:
 		case IROp::Downcount:
-		case IROp::ZeroFpCond:
 			if (queuing) {
 				// These are freebies.  Sometimes helps with delay slots.
 				otherQueue.push_back(inst);
diff --git a/Core/MIPS/RiscV/RiscVCompSystem.cpp b/Core/MIPS/RiscV/RiscVCompSystem.cpp
index c6c0070751..dbfa392a2b 100644
--- a/Core/MIPS/RiscV/RiscVCompSystem.cpp
+++ b/Core/MIPS/RiscV/RiscVCompSystem.cpp
@@ -105,16 +105,17 @@ void RiscVJitBackend::CompIR_Transfer(IRInst inst) {
 		FMV(FMv::X, FMv::W, gpr.R(IRREG_VFPU_CTRL_BASE + inst.dest), fpr.R(inst.src1));
 		break;
 
+	case IROp::FpCondFromReg:
+		gpr.MapDirtyIn(IRREG_FPCOND, inst.src1);
+		MV(gpr.R(IRREG_FPCOND), gpr.R(inst.src1));
+		break;
+
 	case IROp::FpCondToReg:
 		gpr.MapDirtyIn(inst.dest, IRREG_FPCOND);
 		MV(gpr.R(inst.dest), gpr.R(IRREG_FPCOND));
 		gpr.MarkDirty(gpr.R(inst.dest), gpr.IsNormalized32(IRREG_FPCOND));
 		break;
 
-	case IROp::ZeroFpCond:
-		gpr.SetImm(IRREG_FPCOND, 0);
-		break;
-
 	case IROp::FpCtrlFromReg:
 		gpr.MapDirtyIn(IRREG_FPCOND, inst.src1, MapType::AVOID_LOAD_MARK_NORM32);
 		LI(SCRATCH1, 0x0181FFFF);
diff --git a/Core/MIPS/x86/IRToX86.cpp b/Core/MIPS/x86/IRToX86.cpp
index f543025cdb..a9ba6761b9 100644
--- a/Core/MIPS/x86/IRToX86.cpp
+++ b/Core/MIPS/x86/IRToX86.cpp
@@ -259,6 +259,7 @@ void IRToX86::ConvertIRToNative(const IRInst *instructions, int count, const u32
 			// Cross moves
 		case IROp::FMovFromGPR:
 		case IROp::FMovToGPR:
+		case IROp::FpCondFromReg:
 		case IROp::FpCondToReg:
 		case IROp::VfpuCtrlToReg:
 
@@ -266,7 +267,6 @@ void IRToX86::ConvertIRToNative(const IRInst *instructions, int count, const u32
 		case IROp::SetCtrlVFPU:
 		case IROp::SetCtrlVFPUReg:
 		case IROp::SetCtrlVFPUFReg:
-		case IROp::ZeroFpCond:
 
 			// Block Exits
 		case IROp::ExitToConst: