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Merge pull request #4456 from unknownbrackets/vertex-decoder-jit

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Fix LDRH emitter bug, use STMIA where possible
This commit is contained in:
Henrik Rydgård committed 2013-11-05 01:35:06 -08:00
2 parents 5886ccffdc c7edf73cdb
commit 246b856e4f
2 files changed
+16 -17
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Common/ArmEmitter.cpp
+1 -1
View File
@@ -816,7 +816,7 @@ void ARMXEmitter::WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 Rm, bool R
Data = abs(Temp);
// The offset is encoded differently on this one.
if (SpecialOp)
Data = (Data & 0xF0 << 4) | (Data & 0xF);
Data = ((Data & 0xF0) << 4) | (Data & 0xF);
if (Temp >= 0) Add = true;
}
break;
GPU/GLES/VertexDecoder.cpp
+15 -16
View File
@@ -1034,16 +1034,13 @@ void VertexDecoderJitCache::Jit_NormalS16() {
}
void VertexDecoderJitCache::Jit_NormalFloat() {
//ADD(scratchReg, srcReg, dec_->nrmoff);
//LDMIA(scratchReg, false, 3, tempReg1, tempReg2, tempReg3);
//ADD(scratchReg, dstReg, dec_->decFmt.nrmoff);
//STMIA(scratchReg, false, 3, tempReg1, tempReg2, tempReg3);
// Might not be aligned to 4, so we can't use LDMIA.
LDR(tempReg1, srcReg, dec_->nrmoff);
LDR(tempReg2, srcReg, dec_->nrmoff + 4);
LDR(tempReg3, srcReg, dec_->nrmoff + 8);
STR(tempReg1, dstReg, dec_->decFmt.nrmoff);
STR(tempReg2, dstReg, dec_->decFmt.nrmoff + 4);
STR(tempReg3, dstReg, dec_->decFmt.nrmoff + 8);
// But this is always aligned to 4 so we're safe.
ADD(scratchReg, dstReg, dec_->decFmt.nrmoff);
STMIA(scratchReg, false, 3, tempReg1, tempReg2, tempReg3);
}
// Through expands into floats, always. Might want to look at changing this.
@@ -1078,23 +1075,20 @@ void VertexDecoderJitCache::Jit_PosS8() {
// Copy 6 bytes and then 2 zeroes.
void VertexDecoderJitCache::Jit_PosS16() {
LDR(tempReg1, srcReg, dec_->posoff);
LDR(tempReg2, srcReg, dec_->posoff + 4); // WARNING: This SHOULD be an LDRH but things break! why?
LDRH(tempReg2, srcReg, dec_->posoff + 4);
STR(tempReg1, dstReg, dec_->decFmt.posoff);
STR(tempReg2, dstReg, dec_->decFmt.posoff + 4);
}
// Just copy 12 bytes.
void VertexDecoderJitCache::Jit_PosFloat() {
//ADD(scratchReg, srcReg, dec_->posoff);
//LDMIA(scratchReg, false, 3, tempReg1, tempReg2, tempReg3);
//ADD(scratchReg, dstReg, dec_->decFmt.posoff);
//STMIA(scratchReg, false, 3, tempReg1, tempReg2, tempReg3);
// Might not be aligned to 4, so we can't use LDMIA.
LDR(tempReg1, srcReg, dec_->posoff);
LDR(tempReg2, srcReg, dec_->posoff + 4);
LDR(tempReg3, srcReg, dec_->posoff + 8);
STR(tempReg1, dstReg, dec_->decFmt.posoff);
STR(tempReg2, dstReg, dec_->decFmt.posoff + 4);
STR(tempReg3, dstReg, dec_->decFmt.posoff + 8);
// But this is always aligned to 4 so we're safe.
ADD(scratchReg, dstReg, dec_->decFmt.posoff);
STMIA(scratchReg, false, 3, tempReg1, tempReg2, tempReg3);
}
#elif defined(_M_X64) || defined(_M_IX86)
@@ -1278,10 +1272,15 @@ void VertexDecoderJitCache::Jit_TcU16Through() {
}
void VertexDecoderJitCache::Jit_TcFloatThrough() {
#ifdef _M_X64
MOV(64, R(tempReg1), MDisp(srcReg, dec_->tcoff));
MOV(64, MDisp(dstReg, dec_->decFmt.uvoff), R(tempReg1));
#else
MOV(32, R(tempReg1), MDisp(srcReg, dec_->tcoff));
MOV(32, R(tempReg2), MDisp(srcReg, dec_->tcoff + 4));
MOV(32, MDisp(dstReg, dec_->decFmt.uvoff), R(tempReg1));
MOV(32, MDisp(dstReg, dec_->decFmt.uvoff + 4), R(tempReg2));
#endif
}
void VertexDecoderJitCache::Jit_Color8888() {
@@ -1474,7 +1473,7 @@ void VertexDecoderJitCache::Jit_PosFloat() {
bool VertexDecoderJitCache::CompileStep(const VertexDecoder &dec, int step) {
// See if we find a matching JIT function
for (int i = 0; i < ARRAY_SIZE(jitLookup); i++) {
for (size_t i = 0; i < ARRAY_SIZE(jitLookup); i++) {
if (dec.steps_[step] == jitLookup[i].func) {
((*this).*jitLookup[i].jitFunc)();
return true;