Jake.Stine 1698382065 Simplified CPU-level exception behavior:
* Both INTC and DMAC exceptions are now issued together when possible (0x400 | 0x800 to the CAUSE register, respectively)
 * CPU exceptions are checked on every event now, instead of using scheduled interrupts on bits 30/31.  This removes the need to constantly reschedule events during interrupt-disabled states.
 * CPU exception test is moved to the top of the EE event test.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3728 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-09-05 15:11:19 +00:00
2010-08-27 13:48:41 +00:00
2010-08-17 14:39:58 +00:00
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PCSX2 - The Playstation 2 Emulator
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