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Common: Switch movmsk to auto SSE/AVX

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This commit is contained in:
TellowKrinkle
2025-08-09 23:43:16 -05:00
committed by TellowKrinkle
parent 7cc8e5887f
commit 8dc905e827
3 changed files with 23 additions and 10 deletions
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common/emitter/instructions.h
+6 -5
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@@ -475,12 +475,13 @@ namespace x86Emitter
extern void xMOVNTPD(const xIndirectVoid& dst, const xRegisterSSE& src);
extern void xMOVNTPS(const xIndirectVoid& dst, const xRegisterSSE& src);
extern void xMOVMSKPS(const xRegister32& to, const xRegisterSSE& from);
extern void xMOVMSKPD(const xRegister32& to, const xRegisterSSE& from);
extern void xMOVMSKPS(const xRegister32& dst, const xRegisterSSE& src);
extern void xMOVMSKPD(const xRegister32& dst, const xRegisterSSE& src);
extern void xMASKMOV(const xRegisterSSE& to, const xRegisterSSE& from);
extern void xPMOVMSKB(const xRegister32or64& to, const xRegisterSSE& from);
extern void xPALIGNR(const xRegisterSSE& to, const xRegisterSSE& from, u8 imm8);
extern void xMASKMOV(const xRegisterSSE& dst, const xRegisterSSE& src);
extern void xPMOVMSKB(const xRegister32or64& dst, const xRegisterSSE& src);
extern void xPALIGNR(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2, u8 imm8);
static void xPALIGNR(const xRegisterSSE& dst, const xRegisterSSE& src, u8 imm8) { xPALIGNR(dst, dst, src, imm8); }
// ------------------------------------------------------------------------
common/emitter/simd.cpp
+5 -5
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@@ -837,15 +837,15 @@ namespace x86Emitter
// ------------------------------------------------------------------------
__fi void xMOVMSKPS(const xRegister32& to, const xRegisterSSE& from) { xOpWrite0F(0x50, to, from); }
__fi void xMOVMSKPD(const xRegister32& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0x50, to, from, true); }
__fi void xMOVMSKPS(const xRegister32& dst, const xRegisterSSE& src) { EmitSIMD(SIMDInstructionInfo(0x50).mov(), dst, dst, src); }
__fi void xMOVMSKPD(const xRegister32& dst, const xRegisterSSE& src) { EmitSIMD(SIMDInstructionInfo(0x50).mov().p66(), dst, dst, src); }
// xMASKMOV:
// Selectively write bytes from mm1/xmm1 to memory location using the byte mask in mm2/xmm2.
// The default memory location is specified by DS:EDI. The most significant bit in each byte
// of the mask operand determines whether the corresponding byte in the source operand is
// written to the corresponding byte location in memory.
__fi void xMASKMOV(const xRegisterSSE& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0xf7, to, from); }
__fi void xMASKMOV(const xRegisterSSE& dst, const xRegisterSSE& src) { EmitSIMD(SIMDInstructionInfo(0xf7).mov().p66(), dst, dst, src); }
// xPMOVMSKB:
// Creates a mask made up of the most significant bit of each byte of the source
@@ -855,13 +855,13 @@ namespace x86Emitter
// When operating on a 64-bit (MMX) source, the byte mask is 8 bits; when operating on
// 128-bit (SSE) source, the byte mask is 16-bits.
//
__fi void xPMOVMSKB(const xRegister32or64& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0xd7, to, from); }
__fi void xPMOVMSKB(const xRegister32or64& dst, const xRegisterSSE& src) { EmitSIMD(SIMDInstructionInfo(0xd7).mov().p66(), dst, dst, src); }
// [sSSE-3] Concatenates dest and source operands into an intermediate composite,
// shifts the composite at byte granularity to the right by a constant immediate,
// and extracts the right-aligned result into the destination.
//
__fi void xPALIGNR(const xRegisterSSE& to, const xRegisterSSE& from, u8 imm8) { xOpWrite0F(0x66, 0x0f3a, to, from, imm8); }
__fi void xPALIGNR(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2, u8 imm8) { EmitSIMD(SIMDInstructionInfo(0x0f).i().p66().m0f3a(), dst, src1, src2, imm8); }
// --------------------------------------------------------------------------------------
tests/ctest/common/x86emitter/codegen_tests_main.cpp
+12
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@@ -414,6 +414,12 @@ TEST(CodegenTests, SSETest)
CODEGEN_TEST(xMOVNTDQA(ptr[r9], xmm3), "66 41 0f e7 19");
CODEGEN_TEST(xMOVNTPD(ptr[rax], xmm4), "66 0f 2b 20");
CODEGEN_TEST(xMOVNTPS(ptr[rcx], xmm8), "44 0f 2b 01");
CODEGEN_TEST(xMOVMSKPS(ecx, xmm8), "41 0f 50 c8");
CODEGEN_TEST(xMOVMSKPD(r8d, xmm2), "66 44 0f 50 c2");
CODEGEN_TEST(xPMOVMSKB(eax, xmm2), "66 0f d7 c2");
CODEGEN_TEST(xPALIGNR(xmm4, xmm8, 1), "66 41 0f 3a 0f e0 01");
CODEGEN_TEST(xMASKMOV(xmm2, xmm9), "66 41 0f f7 d1");
}
TEST(CodegenTests, AVXTest)
@@ -694,6 +700,12 @@ TEST(CodegenTests, AVXTest)
CODEGEN_TEST(xMOVNTPD(ptr[rax], xmm4), "c5 f9 2b 20");
CODEGEN_TEST(xMOVNTPS(ptr[rcx], xmm8), "c5 78 2b 01");
CODEGEN_TEST(xMOVMSKPS(ecx, xmm8), "c4 c1 78 50 c8");
CODEGEN_TEST(xMOVMSKPD(r8d, xmm2), "c5 79 50 c2");
CODEGEN_TEST(xPMOVMSKB(eax, xmm2), "c5 f9 d7 c2");
CODEGEN_TEST(xPALIGNR(xmm4, xmm8, 1), "c4 c3 59 0f e0 01");
CODEGEN_TEST(xMASKMOV(xmm2, xmm9), "c4 c1 79 f7 d1");
CODEGEN_TEST(xVMOVAPS(xmm0, xmm1), "c5 f8 28 c1");
CODEGEN_TEST(xVMOVAPS(xmm0, ptr32[rdi]), "c5 f8 28 07");
CODEGEN_TEST(xVMOVAPS(ptr32[rdi], xmm0), "c5 f8 29 07");